• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1915-1920
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• 2015

ISO 26262 is an international standard for the functional safety of electric and electronic systems in vehicles, and this standard has become a major issue in the automotive industry. In this paper, a functional safety compliant electronic control unit (ECU) for an electric power steering (EPS) system and a demonstration purposed EPS system are developed, and a software and hardware structure for a safety critical system is presented. EPS is the most recently introduced power steering technology for vehicles, and it can improve driver’s convenience and fuel efficiency. In conformity with the design process specified in ISO 26262, the Automotive Safety Integrity Level (ASIL) of an EPS system is evaluated, and hardware and software are designed based on an asymmetric dual processing unit architecture and an external watchdog. The developed EPS system effectively demonstrates the fault detection and diagnostic functions of a functional safety compliant ECU as well as the basic EPS functions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.203-211
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• 2012

This paper proposes a $16{\times}16$ and $32{\times}32$ inverse transform architecture for HEVC (High Efficiency Video Coding). HEVC large transform of $16{\times}16$ and $32{\times}32$ suffers from huge computational complexity. To resolve this problem, we proposed a new large inverse transform architecture based on hardware reuse. The processing element is optimized by exploiting fully recursive and regular butterfly structure. To achieve low area, the processing element is implemented by shifters and adders without multiplier. Implementation of the proposed 2-D inverse transform architecture in 0.18 ${\mu}m$ technology shows about 300 MHz frequency and 287 Kgates area, which can process 4K ($3840{\times}2160$)@ 30 fps image.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.34-42
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• 2013

Human faces have been broadly studied in digital image and video processing fields. An appearance-based method, the adaptive boosting learning algorithm using integral image representations has been successfully employed for face detection, taking advantage of the feature extraction's low computational complexity. In this paper, we propose a face-detection postprocessing method that equalizes instantaneous facial regions in an efficient hardware architecture for use in real-time multimedia applications. The proposed system requires low hardware resources and exhibits robust performance in terms of the movements, zooming, and classification of faces. A series of experimental results obtained using video sequences collected under dynamic conditions are discussed.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2827-2829
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• 1999

Genetic algorithms were described as a method of solving large-scaled optimization problems with complex constraints. It has overcome their slowness, a major drawback of genetic algorithms using hardware implementation of genetic algorithm processor (GAP). In this study, we proposed GAP effectively connecting the goodness of survival-based GA, steady-state GA, tournament selection. Using Pipeline Parallel processing, handshaking protocol effectively, the proposed GAP exhibits 50% speed-up over survival-based GA which runs one million crossovers per second(1MHz). It will be used for high speed processing such of central processor of EHW, robot control and many optimization problem.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.1072-1079
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• 2014

This paper introduces a coordinated droop control for the stand-alone DC micro-grid, which is composed of photo-voltaic generator, wind power generator, engine generator, and battery storage with SOC (state of charge) management system. The operation of stand-alone DC micro-grid with the coordinated droop control was analyzed with computer simulation. Based on simulation results, a hardware simulator was built and tested to analyze the performance of proposed system. The developed simulation model and hardware simulator can be utilized to design the actual stand-alone DC micro-grid and to analyze its performance. The coordinated droop control can improve the reliability and efficiency of the stand-alone DC micro-grid.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.785-792
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• 2010

This paper on the Research of Naval Electronic Warfare System HILS(Hardware In the Loop System) describes the EW engagement HILS construction method for evaluation of the operational concept analysis on active RF Decoy in staying in the air and the deceit ability to anti-ship missile seeker. We obtain the EW M&S technology of EW engagement HILS and EW efficiency analysis from this project. This Naval Electronic Warfare System HILS technology will support Active Decoy Development Project and any other HILS of EW weapon in KOREA ARMY/NAVY/AIR FORCE.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.615-618
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• 2000

A number of studies have recently been made on hardware for a biological neuron f3r application with information processing functions of neural networks. We have been trying to produce hardware from the viewpoint that development of a new hardware neuron model is one of the important problems in the study of neural networks. In this paper, we first discuss the circuit structure of a pulse-type hardware neuron model with the enhancement-mode MOSFETs (E-MOSFETs). And we construct a pulse-type hardware neuron model using I-MOSFETs. As a result, it is shown that our proposed new model can exhibit firing phenomena even if the power supply voltage becomes less than 1.5[V]. So it is verified that our model is profitable for IC.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.3
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• pp.121-125
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• 2014

A hardware implementation of Hilbert transform is indespensible element in DSP system, but it suffers form a high complexity of system level hardware resulted in a large amount of the used gate. In this paper, we implemented the Hilbert transformer using MAG algorithm that reduces the complexity of hardware.