• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.18-21
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• 2020

Undetected wafer slip during the lift pin-down motion in semiconductor equipment may affect the center to edge variation, wafer warpage, and pattern misalignment in plasma equipment. Direct measuring of the amount of wafer slip inside the plasma process chamber is not feasible because of the hardware space limitation inside the plasma chamber. In this paper, we demonstrated a practice for the wafer lift pin-up and down motions with respect to the gear ratio, operating voltage, and pulse width modulation to maintain accurate wafer position using remote control linear servo motor with an experimentally designed chamber mockup. We noticed that the pin moving velocity and gear ratio are the most influencing parameters to be control, and the step-wised position control algorithm showed the most suitable for the reduction of wafer slip.

• Smart Structures and Systems
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• v.29 no.6
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• pp.791-797
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• 2022

A complex system is comprised of numerous entities containing physical components, devices and hardware, events or phenomena, and subsystems, there are intricate interactions among these entities. To reasonably identify the critical fault propagation paths, a system fault propagation model is essential based on the system failure mechanism and failure data. To establish an appropriate mathematical model for the complex system, these entities and their complicated relations must be represented objectively and reasonably based on the structure. Taking a command and control system as an example, this paper proposes a hierarchical fault propagation analysis method, analyzes and determines the edge betweenness ranking model and the importance degree of each sub-system.

• Journal of Korea Multimedia Society
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• v.24 no.12
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• pp.1606-1613
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• 2021

Recently various attempts to control hardware through integration of sensors and artificial intelligence have been made. This paper proposes a smart hazardous sound detection at home. Previous sound recognition methods have problems due to the processing of background sounds and the low recognition accuracy of high-frequency sounds. To get around these problems, a new MFCC(Mel-Frequency Cepstral Coefficient) algorithm using Wiener filter, modified filterbank is proposed. Experiments for comparing the performance of the proposed method and the original MFCC were conducted. For the classification of feature vectors extracted using the proposed MFCC, DNN(Deep Neural Network) was used. Experimental results showed the superiority of the modified MFCC in comparison to the conventional MFCC in terms of 1% higher training accuracy and 6.6% higher recognition rate.

• International Journal of Control, Automation, and Systems
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• v.1 no.3
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• pp.339-350
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• 2003

In this paper, we propose a simultaneous multithreading (SMT) architecture that improves instruction throughput by exploiting instruction level parallelism (ILP) and thread level parallelism (TLP). The proposed architecture issues and completes instructions belonging to the same thread in exact program order. The issue and completion policy greatly reduces the design complexity and hardware cost of our architecture, compared with others that employ out-of-order issue and completion. On the other hand, when the instructions belong to different threads, the issue and completion orders for those instructions may not necessarily be identical to the fetch order. The processor issues instructions simultaneously from multiple threads to functional units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably improves performance and resource utilization with minimal additional hardware cost over the conventional superscalar processors. This paper proposes an SMT architecture with grouping as well as one without grouping. Without grouping, all threads dynamically and flexibly share most resources. On the other hand, in the SMT architecture with grouping, in which resources and threads are divided into several groups for design simplification, resources are shared only among threads belonging to the same group as those resources. Simulation results show that our processors with four and eight threads improve performance by three or more times over the conventional superscalar processor with comparable execution resources and policies, and that reasonable grouping reduces the design complexity of SMT processors with little negative effect on performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.27-34
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• 2012

In this paper, the implementation of high throughput two-dimensional (2-D) $8{\times}8$ forward and inverse integer DCT transform for H.264 is presented. The forward and inverse transforms are represented using simple shift and addition operations. Matrix decomposition and matrix operation such as the Kronecker product and direct sum are used to reduce the computation complexity. The proposed design uses integer computations and does not use transpose memory and hence, the resource consumption is also reduced. The maximum operating frequency of the proposed pipelined architecture is 1.184 GHz, which achieves 25.27 Gpixels/sec throughput rate with the hardware cost of 44864 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.940-947
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• 2015

This paper presents the region of interest pattern image extraction method on a display printed matrix pattern. Proposed method can not use conventional method such as laser, ultrasonic waves and touch sensor. It searches feature point and rotation angle using luminance and pattern reliable feature points of input image, and then it extracts region of interest. In order to extract region of interest, we simulate proposed method using pattern image written various angles on display panel. The proposed method makes progress using the OpenCV and the window program, and was designed using Verilog-HDL and was verified through the FPGA Board(xc6vlx760) of Xilinx.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.103-108
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• 2014

In the virtualized server systems, a scheduler in a hypervisor is responsible to assign physical resources for virtual machines. However, the traditional scheduler is hard to provide optimized resource allocation considering the amount of I/O requests. Especially, the drawback hinders performance of software load balancer which runs on virtual machines to distribute I/O requests from the clients. In this paper, we propose a new architecture to improve the performance of software load balancer using multiprocess. Our architecture aims to improve hardware resource utilization and overall performance of the server systems which utilize virtualization technology. Experimental results show the effectiveness of the proposed architecture for the various cases.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.6
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• pp.673-681
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• 2005

As it is the most important to make sure security and reliability for nuclear Power Plant, it's considered the most crucial issues to develop a fault detective and diagnostic system in spite of multiple hardware redundancy in itself. To develop an algorithm for a fault diagnosis in the nuclear PWR steam generator, this paper proposes a method based on ART2(adaptive resonance theory 2) neural network that senses and classifies troubles occurred in the system. The fault diagnosis system consists of fault detective part to sense occurred troubles, parameter estimation part to identify changed system parameters and fault classification part to understand types of troubles occurred. The fault classification part Is composed of a fault classifier that uses ART2 neural network. The Performance of the proposed fault diagnosis a18orithm was corroborated by applying in the steam generator.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.72-79
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• 2011

The importance of parallel programming seriously emerges ever since the modern microprocessor architecture has been shifted to the multi-core system. Transactional Memory has been proposed to address synchronization which is usually implemented by using locks. However, the lock based synchronization method reduces the parallelism and has the possibility of causing deadlock. In this paper, we propose an efficient method to utilize transactional memory for the situation which has high contention. The proposed idea is based on the theoretical analysis and it is verified with simulation results. The simulation environment has been implemented using HTM(Hardware Transactional Memory) systems. We also propose a model of the dining philosopher problem to discuss the efficient resource management using the transactional memory technique.