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Multi -Core Transactional Memory for High Contention Parallel Processing  

Kim, Seung-Hun (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Sun-Woo (Department of Electrical and Electronic Engineering, Yonsei University)
Ro, Won-Woo (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.48, no.1, 2011 , pp. 72-79 More about this Journal
Abstract
The importance of parallel programming seriously emerges ever since the modern microprocessor architecture has been shifted to the multi-core system. Transactional Memory has been proposed to address synchronization which is usually implemented by using locks. However, the lock based synchronization method reduces the parallelism and has the possibility of causing deadlock. In this paper, we propose an efficient method to utilize transactional memory for the situation which has high contention. The proposed idea is based on the theoretical analysis and it is verified with simulation results. The simulation environment has been implemented using HTM(Hardware Transactional Memory) systems. We also propose a model of the dining philosopher problem to discuss the efficient resource management using the transactional memory technique.
Keywords
Transactional Memory; Multi-Core; Parallel processing; Synchronization; Multi-Threading;
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