• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.95-98
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• 2004

In this paper, the hardware design of a transmission convergence sublayer(TC) for boradband wireless access system is described, which performs (1) formatting TC PDUs to MAC PDUs, (2) RS encoding/decoding, (3) providing various control signal to PHY modem. The TC hardware has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.448-451
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• 2003

For this research, we developed the hardware and software of the measurement system for on-line test and evaluation. The software controls the hardware of the measurement data and acts as interface between users and the system hardware. In this paper, we is studied for temperature measurement of main transformer. In order to this test is developed measurement system. Using this system, we obtained important result for main transformer temperature.

• Journal of IKEEE
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• v.25 no.1
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• pp.10-14
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• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.

• Journal of IKEEE
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• v.18 no.4
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Journal of Power Electronics
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• v.6 no.2
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• International journal of advanced smart convergence
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• v.9 no.4
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• pp.62-73
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• 2020

In this paper, we present electronic acupuncture needles we have developed using intelligence technology based on Bluetooth in order to allow anyone to simply receive customized remote diagnosis and treatment by clicking on the menu of the smartphone regardless of time and place. In order to determine the health condition and disease of patients, we have developed a software and a hardware of electronic acupuncture needles, operating on Bluetooth which transmits biometric data to oriental medical doctors using the functions of automatically determining pulse diagnosis, tongue diagnosis, and oxygen saturation; the functions are most commonly used in herbal treatment. In addition, using fuzzy logic and reasoning based on smartphones, we present in this paper an algorithm and the results of completion of hardware implementation for electronic acupuncture needles, appropriate for the body conditions of patients; the algorithm and the hardware implementation are for a treatment time duration by electronic acupuncture needles, an automatic determinations of pulse diagnosis, tongue diagnosis, and oxygen saturation, a function implementation for automatic display of acupuncture point, and a strength adjustment of electronic acupuncture needles. As a result of our simulation, we have shown that the treatment of patients, performed using an Electronic Acupuncture Needles based on intelligence, is more efficient compared to the treatment that was performed before.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.9
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• pp.1373-1378
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• 2017

This paper presents a basic ECU(Electronic Control Unit) hardware development procedure for the functional safety of in-vehicle network systems. We consider complete hardware redundancy as a safety mechanism for in-vehicle communication network under the assumption of the wired network failure such as disconnection of a CAN bus. An ESC (Electronic Stability Control) system is selected as an item and the required ASIL(Automotive Safety Integrity Level) for this item is assigned by performing the HARA(Hazard Analysis and Risk Assessment). The basic hardware architecture of the ESC system is designed with a microcontroller, passive components, and communication transceivers. The required ASIL for ESC system is shown to be satisfied with the designed safety mechanism by calculation of hardware architecture metrics such as the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.12
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.