• Journal of Institute of Control, Robotics and Systems
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• v.14 no.5
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• pp.420-425
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• 2008

PMMA light guiding plate with nano-sized pattern was fabricated using anodized aluminum oxide membrane as a template for nano imprint lithography. Nano-sized pore arrays were prepared by the self-organization processes of the anodic oxidation using the aluminum plate with 99.999% purity. Since the aluminum plate has a rough surface, the aluminum plate with thickness of 1mm was anodized after the pre-treatments of chemical polishing, and electrochemical polishing. The surface morphology of the alumina obtained by the first anodization process was controlled by the concentration of electrochemical solution during the first anodization. The surface morphology of the alumina was also changed according to temperature of the solution during chemical polishing performed after first anodization. The pore widening process was employed for obtaining the one-channel with flat surface and height of the channel because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of two-channel with rough surface. It is shown from SPM results that the nano-sized pattern on PMMA light guiding plate fabricated by nano imprint lithography method was well transferred from that of anodized aluminum oxide template.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.81-81
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• 2007

Chemical mechanical polishing (CMP) 공정은 deep 서브마이크론 집적회로의 다층배선구조률 실현하기 위해 inter-metal dielectric (IMD), inter-layer dielectric layers (ILD), pre-metal dielectric (PMD) 층과 같은 절연막 외에도 W, Al, Cu와 같은 금속층을 평탄화 하는데 효과적으로 사용되고 있으며, 다양한 소자 제작 및 새로운 물질 등에도 광범위하게 응용되고 있다. 하지만 Cu damascene 구조 제작으로 인한 CMP 응용 과정에서, 기계적으로 깨지기 쉬운 65 nm의 소자 이하의 구조에서 새로운 저유전상수인 low-k 물질의 도입으로 인해 낮은 하력의 기계적 연마가 필요하게 되었다. 본 논문에서는 전기화학적 기계적 연마 적용을 위해, I-V 특성 곡선을 이용하여 active, passive, transient, trans-passive 영역의 전기화학적 특성을 알아보았으며, Cu 막의 표면 형상을 알아보기 위해 scanning electron microscopy (SEM) 측정과 energy dispersive spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.544-544
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• 2008

Metal-CMP 공정시 높은 압력을 가해 줌으로 인하여 금속배선의 디싱 현상과 에로젼 현상이 발생하고 다공성의 하부층에 균열이 생기는 문제점을 개선하고자, 낮은 하력에서 금속막의 광역 평탄화를 이룰 수 있는 ECMP(Electrochemical Chemical Mechanical Polishing)가 생겨나게 되었다. 본 논문에서는 다양한 전해액의 전류-전압 특성 곡선을 비교 분석하여, 패시베이션막이 형성되는 곳을 알 수 있었고, CV와 LSV 법을 통해 전기화학적인 특성을 고찰하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.6
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• pp.239-244
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• 2005

Nano-sizedporearrayswerepreparedbytheself-organizationprocessesoftheanodicoxidationusingthealuminumplatewith99.999$\%$purity.Sincethealuminumplatehasaroughsurface,thealuminumplateof1mmthicknesswasanodizedafterthepre-treatmentsofpressing,mechanicalpolishing,thermaloxidation,chemicalpolishing,andelectrochemicalpolishing.Thediameterofthenano-sizedporesandthethicknessofbarrierlayercanbecontrolledbyappliedvoltage.Thethicknessofaluminamembranecanalsobecontrolledbytheanodizingcurrent.Thenano-sizedporeswithdiameterof60$\~$120nm,thedistancebetweenthenearestporesof30$\~$60nm,andthethicknessof6$\~$7Wwereobtainedbytheanodicoxidationprocess.Theporewideningprocesswasemployedforobtainingtheone-channelwithflatsurfacebecausetheporesofthealuminamembranepreparedbythefixedvoltagemethodshowsthestructureoftwo-channelwithroughsurface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.126-129
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point, the passivation potential (PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.583-586
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• 2000

The non-selective method by polishing after grinding was used widely to thinning of SDB SOI structures. This method was very difficult to thickness control of thin film, and it was dependent on equipments. However electrochemical etch-stop, one of the selective methods, was able to accurately thickness control and etch equipment was very simple. Therefore, this paper described with the effect of leakage current and electrodes on electrochemical etch-stop. Consequentially, PP(passivation potential) was changed according to the kinds of contact and contact sizes, but OCP(open current potential) was not change with range of -1.5~-1.3V

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.431-436
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.57-58
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• 2006

Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.937-938
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.207-208
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• 2013