• 한국자동차공학회논문집
• /
• 제21권2호
• /
• pp.159-165
• /
• 2013

ESD damage by Charged Cable Model (CCM) is introduced. Due to its own impedance characteristic unlike Human Body Model (HBM) or Machine Model (MM) electric component can be destroyed even though it is located after typical protection circuit. Possible mechanism of ESD damage to automotive electric control unit (ECU) in vehicle environment by CCM discharge was investigated. Based on investigation, field-returned vehicle whose ECU is expected to be damaged by CCM discharge was tested to reproduce it and similar electric component destruction inside ECU was observed. Suggestions to reduce the possibility of ESD damage by CCM are introduced.

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2002년도 학술대회논문집
• /
• pp.105-109
• /
• 2002

A TVS and Varistor are preservative equipment against electro static discharge(ESD). We use a TVS for I/O protection of a circuit which has faster response time than a Varistor. And a Varistor has large power capability, therefore, which be used in input stage for internal pressure prevention. This paper will compare a TVS with a Varistor with respect to response characteristic to ESD in DC 24[V] low voltage circuit.

• 한국신뢰성학회:학술대회논문집
• /
• 한국신뢰성학회 2011년도 춘계학술발표대회 논문집
• /
• pp.119-123
• /
• 2011

Through the test of ESD(Electro Static Discharge) for PCB circuit, we are able to research on the ESD effect. This paper also study on the ESD test method for measurement. It is interesting to compare their characteristics on and the other method.

• 한국신뢰성학회지:신뢰성응용연구
• /
• 제11권3호
• /
• pp.245-249
• /
• 2011

Through the test of ESD(Electro Static Discharge) for PCB circuit, we are able to research on the ESD effect. This paper also studys on the ESD test method for measurement. In the measurement of the discharge current, we used current probe(TC-1). The applied voltage to the PCB metal is -3 kV HBM mode. In conclusion ESD influences exponentially greater impact in nearer PCB circuit.

• Journal of Advanced Marine Engineering and Technology
• /
• 제17권4호
• /
• pp.87-99
• /
• 1993

Nowadays, the cartridge valve can be controlled proportionally in remote place by adopting proportional solenoid and it becomes widely used as control component in hydraulic systems. Especially, multi stage proportional valve is attractive because it consumes less input power though its characteristics might slightly be defected. But, the system parameter should be carefully chosen to obtain optimistic characteristics. This study concerning three stage proportional throttle control valve is purposed to examine the influences of paameters to the dynamic characteristics. The typical transient and frequency responses of proportional throttle control valve were inspected through the experiments and compared to those derived from the theoritical analyses. And it was confirmed that the analyses are appropriate. Then the influences of various system parameters to the dynamic characteristics were examined by means of simulations. For the analyses, the basic equations derived from lumped model were linearized and the linearized equations were transformed to the transfer functions between inputs and outputs. Then the transient responses and frequency responses were obtained from transfer functions. 1. It is appropriate to estimate the dynamic characteristics of valve which has relatively sophisticated structure by means of system analyses using linearized equations. 2. Though the valve has two pilot stages, fairly good characteristics can be obtained by carefully choosing system parameters. 3. Main valve very quickly follows the movement of second pilot valve when the parameters of main valve(the oil supply passage and discharge passage fpr second pilot valve) are appropriately chosen.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.731-734
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.805-808
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.203.1-203.1
• /
• 2016

Poly etch 설비에서 발생하는 dechuck 불량에 의한 Dynamic Alignment(DA) error는 poly etch 설비에서의 고질 적인 문제이다. 발생 원인은 ElectroStatic Chuck(ESC)의 노후화 혹은process plasma에 의한 attack 등으로 ESC와 wafer간 dechucking이 진행될 때 wafer내의 전하가 완전히 discharge되지 못하여 wafer Sticking에 의한 sliding이 발생되며 심해지면 Dynamic Alignment(DA) Error가 발생한다. DA error 발생 되면 particle down으로 wafer는 scrap 되며 DA error가 지속적으로 발생하는 설비는 ESC 교체를 하고 있다. ESC 교체비용도 매우 크며 교체 전까지 설비가 멈추어있는 시간적인 손실이 발생하게 된다. Dechucking을 진행할 때 Wafer에 잔존하는 전하를 제거 하여 Wafer의 sticking을 줄여 DA error를 근원적으로 방지하기 위해 plasma를 이용하여 wafer와 ESC를 하나의 electric circuit으로 연결시키는 방법으로 wafer에 잔존하는 전하를 제거 시키고자 하였다.

• 전기전자학회논문지
• /
• 제10권2호통권19호
• /
• pp.141-148
• /
• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• 전기전자학회논문지
• /
• 제10권2호통권19호
• /
• pp.149-155
• /
• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.