• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.2
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• pp.185-195
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• 2018

As machines have been automated in the field of industries in recent years, it is a paramount importance to manage and maintain the automation machines. When a fault occurs in sensors attached to the machine, the machine may malfunction and further, a huge damage will be caused in the process line. To prevent the situation, the fault of sensors should be monitored, diagnosed and classified in a proper way. In the paper, we propose a sensor fault detection scheme based on SVM and CNN to detect and classify typical sensor errors such as erratic, drift, hard-over, spike, and stuck faults. Time-domain statistical features are utilized for the learning and testing in the proposed scheme, and the genetic algorithm is utilized to select the subset of optimal features. To classify multiple sensor faults, a multi-layer SVM is utilized, and ensemble technique is used for CNN. As a result, the SVM that utilizes a subset of features selected by the genetic algorithm provides better performance than the SVM that utilizes all the features. However, the performance of CNN is superior to that of the SVM.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.49-58
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• 2006

In this paper, a curve-fitting channel estimation method is proposed for orthogonal frequency division multiplexing (OFDM) system in a time-varying frequency-selective fading channel. The method can greatly improve channel state information (CSI) estimation accuracy by performing smoothing and interpolation through consecutive curve-fitting processes in both time domain and frequency domain. It first evaluates least-squares (LS) estimates using pilot symbols and then the estimates are approximated to a polynomial with proper degree in the LS error sense, starting from one preferred domain in which pilots we densely distributed. Smoothing, interpolation, and prediction are performed subsequently to obtain CSI estimates for data transmission. The channel estimation processes are completed by smoothing and interpolating CSI estimates in the other domain once again using the channel estimates obtained in one domain. The performance of proposed method is influenced heavily on the time variation and frequency selectivity of channel and pilot arrangement. Hence, a proper degree of polynomial and an optimum approximation interval according to various system and channel conditions are required for curve-fitting. From extensive simulation results in various channel environments, we see that the proposed method performs better than the conventional methods including the optimal Wiener filtering method, in terms of the mean square error (MSE) and bit error rate (BER).

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.8
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• pp.8-16
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• 1999

In this paper, the performance of a hybrid DS/SFH-SS(direct-sequence/slow-frequency-hopped spread-spectrum) system with coherent BPSK modulation over Nakagami fading channel in the presence of multiple tone jamming is analyzed. Because the Nakagami m-distribution can describe not only Rayleigh fading but also more general fluctuations involving a specular component by adjusting the value of the fading index m. It is known that for m=1 corresponds to Rayleigh fading, for $1/2{\le}m{\le}1$ corresponds to the worst case fading condition, for m>1 corresponds to Rician fading, and for $m{\to}{\infty}$ corresponds to the nonfading condition. The bit error probability is derived over Nakagami model and numerical evaluations are presented for some combinations of system parameters. The results show that as m increases, the bit error probability is better. Also, at a low JSR(jamming-to-signal power ratio), a pure DS-SS system can achieve lower bit error probability than a hybrid DS/SFH-SS system. But at a high JSR, a hybrid DS/SFH-SS system is shown to be superior to a pure DS-SS system. Therefore, it is demonstrated that without increasing the total system bandwidth, the performance of a hybrid DS/SFH-SS is superior to that of a pure DS-SS system in the presence of multiple tone jamming.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.27-34
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• 2016

In the train system, railway vehicles are connected in a line. Therefore, this feature should be considered in composing network topology in a train system. Besides, inter-car communication should be distinguished from in-car communication. As for the inter-car communication, the hybrid topology was proposed to use rather than the conventional ring, star, daisy-chain, and bus topologies. In the hybrid topology, a number of cars are bound to be a group. Then star topology is used for the communication in a group and daisy-chain topology is used for the communication between groups. Hybrid topology takes the virtue of both star and daisy-chain topologies. Hence it maintains communication speed with reducing the number of connecting cables between cars. Therefore, it is important to choose the number of cars in a group to obtain higher performance. In this paper, we focus on the optimization of hybrid topology for railway cars. We first assume that the size of data and the frequency of data production for each car is identical. We also assume that the importance for the maximum number of cables to connect cars is variable as well as the importance of the communication speed. Separated weights are granted to both importance and we derive the optimum number of cars in a group for various number of cars and weights.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.69-74
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• 2010

A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.65-72
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• 2010

Nowadays, most hospitals have been used to create MRI or CT and managed them. Doctors depend on fast access to images such as magnetic resonance imaging (MRIs), computerized tomography (CT) scans, and X-rays for accurate diagnoses. Those image data are related privacy of a patient. Therefore, it should be protected from hackers and managed perfectly. In this paper, we propose a data hiding method into MRI or CT related a condition and intervention of a patient, and it is suggested that how to authenticate patient information from an image. In this way, we create hash code using HMAC with patient information, and hash code and patient information is hided into an image. After then, doctor will check authentication using HMAC. In addition, we use a reversible data hiding DE(Difference Expansion) algorithm to hide patient information. This technique is possible to reconstruct the original image with stego image. Therefore, doctor can easily be possible to check condition of a patient. As a consequence of an experiment with MRI image, data hiding, extraction and reconstruct is shown compact performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Korean Geophysical Society
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• v.5 no.2
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• pp.111-129
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• 2002

Generally, investigation methods of cut slope are conucted only geological surface survey to gain engineering geological data of cut slopes. These methods have many problems such as limitations of investigation for a special area. So geophysical investigations such as geotomography, seismic and electrical resistivity methods have been used to search for failure surface in potential failure slopes or failed slopes. But investigation method using the borehole camera is recently a used method and it is thought that this method is more reliable method than other investigation methods because of being able to see by the eyes. Therefore, this paper was conducted investigations of borings and BIPS(Borehole Image Processing System) to search for potential sliding surfaces and was applied to obtain information of discontinuity on failed and potential failure slope in highway. As the results of BIPS, we could decide potential sliding surface in the slope, conducted to check slope stability and decided slope stability measures.