• 제목/요약/키워드: Electrical circuit

검색결과 7,395건 처리시간 0.031초

High performance X-band power amplifier MMIC using a 0.25 ㎛ GaN HEMT technology (0.25 ㎛ GaN HEMT 기술을 이용한 우수한 성능의 X-대역 전력 증폭기)

  • Lee, Bok-Hyung;Park, Byung-Jun;Choi, Sun-Youl;Lim, Byeong-Ok;Go, Joo-Seoc;Kim, Sung-Chan
    • Journal of IKEEE
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    • 제23권2호
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    • pp.425-430
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    • 2019
  • This work describes the design and characterization of a X-band power amplifier (PA) monolithic microwave integrated circuit (MMIC) using a $0.25{\mu}m$ gate length gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The developed X-band power amplifier MMIC has small signal gain of over 22.7 dB and saturated output power of 43.02 dBm (20.04 W) over the entire band of 9 to 10 GHz. Maximum saturated output power is a 43.84 dBm (24.21 W) at 9.5 GHz. Its power added efficiency (PAE) is 41.0~51.24% and the chip dimensions are $3.7mm{\times}2.3mm$, generating the output power density of $2.84W/mm^2$. The developed GaN power amplifier MMIC is expected to be applied in a variety of X-band radar applications.

Design of Subthreshold SRAM Array utilizing Advanced Memory Cell (개선된 메모리 셀을 활용한 문턱전압 이하 스태틱 램 어레이 설계)

  • Kim, Taehoon;Chung, Yeonbae
    • Journal of IKEEE
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    • 제23권3호
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    • pp.954-961
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    • 2019
  • This paper suggests an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The memory cell consists of symmetric 8 transistors, in which the latch storing data is controlled by a column-wise assistline. During the read, the data storage nodes are temporarily decoupled from the read path, thus eliminating the read disturbance. Additionally, the cell keeps the noise-vulnerable 'low' node close to the ground, thereby improving the dummy-read stability. In the write, the boosted wordline facilitates to change the contents of the memory bit. At 0.4 V supply, the advanced 8T cell achieves 65% higher dummy-read stability and 3.7 times better write-ability compared to the commercialized 8T cell. The proposed cell and circuit techniques have been verified in a 16-kbit SRAM array designed with an industrial 180-nm low-power CMOS process.

Non-Isolation, High-Efficiency and High-Voltage-Output DC-DC Converter using the Self-Driven Synchronous Switch (자기구동 동기스위치를 이용한 비절연 고효율 고전압출력 DC-DC 컨버터)

  • Jeong, Gang-Youl
    • Journal of IKEEE
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    • 제23권3호
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    • pp.962-970
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    • 2019
  • In this paper, the non-isolation, high-efficiency and high-voltage-output DC-DC converter using the self-driven synchronous switch is proposed. The proposed converter achieves high-voltage-output by applying a tapped inductor to the conventional boost DC-DC converter structure, and it reduces the voltage stress of main switch applying the lossless capacitor-diode (LCD) snubber to the switch. And the proposed converter applies the synchronous switch instead of the diode to the output part, and thus it resolves the reverse recovery problem and achieves high-efficiency. The synchronous switch of proposed converter uses the self-driven method and has a simple structure. In this paper, the operation principle of proposed converter is explained, and then, a design example of the converter prototype is presented. And the characteristics of the proposed converter are shown through experimental results of the prototype made with the designed circuit parameters.

A Lightweight Hardware Implementation of ECC Processor Supporting NIST Elliptic Curves over GF(2m) (GF(2m) 상의 NIST 타원곡선을 지원하는 ECC 프로세서의 경량 하드웨어 구현)

  • Lee, Sang-Hyun;Shin, Kyung-Wook
    • Journal of IKEEE
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    • 제23권1호
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    • pp.58-67
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    • 2019
  • A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

Vibration Reduction of Cantilever using Passive Piezoelectric Shunt (수동형 압전션트를 이용한 외팔보의 진동저감 연구)

  • Yun, Yangsoo;Kim, Jaechul;Noh, Heemin
    • Journal of The Korean Society For Urban Railway
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    • 제6권4호
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    • pp.417-426
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    • 2018
  • Piezoelectric shunt is an electric type damper capable of reducing the vibration of the structure. Vibration generated at the natural frequency of the structure are converted into electrical energy through the piezoelectric material attached to the structure. Electric energy can be dissipated by thermal energy using piezoelectric shunt composed of inductor and resistance to reduce vibration. In this paper, the equation for the optimum inductance required to reduce the vibration of the cantilever beam was examined and the vibration of the aluminum cantilever was reduced by using finite element analysis and experiments. In the finite element analysis, the mode shape and the strain energy distribution were calculated to examine the mounting position, and the vibration reduction of the cantilever was calculated by adjusting the inductance and resistance circuit values. In addition, in the experiment, a variable inductor module was used to reduce the vibration occurring at a specific frequency of the cantilever. Finally, based on the results of the finite element analysis and the experiment, it was verified that the piezoelectric shunt can effectively reduce the vibration of the cantilever.

A Study on Coil Misalignment in a 3-Coil Magnetic Resonance Wireless Power Transmission System of a Electric Vehicle (전기자동차의 3-코일 자기공진방식 무선전력전송 시스템에서 코일의 비 정렬에 관한 연구)

  • Hwang, In-Gab
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • 제14권1호
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    • pp.48-55
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    • 2021
  • The 3-coil magnetic resonance wireless power transmission system was analyzed using an equivalent circuit model, and the |S21| of the system was expressed as the equation of the Q of the three coils, the coupling coefficient k between the transmitting coil and the relay coil, the relay coil and the receiving coil. It is suggested that the maximum efficiency can be obtained when the relay coil is located in the center of the transmitting and the receiving coil. When the distance between the transmitting and the receiving coil is 30 cm and the two coils are aligned, maximum efficiency of 9 % is obtained with the relay coil centered between the coils. If the transmitting coil and the receiving coil are misaligned during a wireless charging of an electric vehicle, the efficiency is expected to decrease significantly compared to the aligned case. It is expected that the efficiency can be increased by using a relay coil and by rotating the coil.

A Study on the Correction of Protection Relay of Temporary Electric Power Installations for Storage Tank (저장 탱크용 임시전력설비의 보호계전기 정정에 관한 연구)

  • Son, Seok-Geum
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • 제13권6호
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    • pp.562-567
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    • 2020
  • In this paper, this is a study on the correction of protection relays to monitor temporary power facilities for storage tanks especially transformers to block and protect faults such as insulation breakdown. When an abnormality such as a short circuit or a ground fault occurs in the power system, it is important to detect this quickly cut off the device and equipment in which the fault occurred and separate it from the power system to correct the protection relay so that it does not interfere with power supply. In addition the fault current calculation that accurately applies the fault type and the cause of the fault for protection cooperation will be the most important factor in the correction of the protection relay. For protection coordination a study was conducted on the method of coordination for protection of power facility protection for storage tanks such as over current relay, ground over current relay, under voltage relay, and ground over voltage relay applied to temporary.

Effect of addition of Tl+ and Pd2+ on the texture and hardness of the non-cyanide gold plating layer (논시안 금도금층의 조직과 경도에 미치는 Tl+ 과 Pd2+ 이온첨가의 영향)

  • Heo, Wonyoung;Son, Injoon
    • Journal of the Korean institute of surface engineering
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    • 제55권6호
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    • pp.460-468
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    • 2022
  • Due to its high electrical conductivity, low contact resistance, good weldability and high corrosion resi-stance, gold is widely used in electronic components such as connectors and printed circuit boards (PCB). Gold ion salts currently used in gold plating are largely cyan-based salts and non-cyanic salts. The cya-nide bath can be used for both high and low hardness, but the non-cyanide bath can be used for low hardness plating. Potassium gold cyanide (KAu(CN)2) as a cyanide type and sodium gold sulfite (Na3[Au(SO)3]2) salt as a non-cyanide type are most widely used. Although the cyan bath has excellent performance in plating, potassium gold cyanide (KAu(CN)2) used in the cyan bath is classified as a poison and a toxic substance and has strong toxicity, which tends to damage the positive photoresist film and make it difficult to form a straight side-wall. There is a need to supplement this. Therefore, it is intended to supplement this with an eco-friendly process using sodium sulfite sodium salt that does not contain cyan. Therefore, the main goal is to form a gold plating layer with a controllable hardness using a non-cyanide gold plating solution. In this study, the composition of a non-cyanide gold plating solution that maintains hardness even after annealing is generated through gold-palladium alloying by adding thallium, a crystal regulator among electrolysis factors affecting the structure and hardness, and changes in plating layer structure and crystallinity before and after annealing the correlation with the hardness.

A Ku-band 3 Watt PHEMT MMIC Power Amplifier for satellite communication applications (위성 통신 응용을 위한 Ku-대역 3 Watt PHEMT MMIC 전력 증폭기)

  • Uhm, Won-Young;Lim, Byeong-Ok;Kim, Sung-Chan
    • Journal of IKEEE
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    • 제24권4호
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    • pp.1093-1097
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    • 2020
  • This work describes the design and characterization of a Ku-band monolithic microwave integrated circuit (MMIC) power amplifier (PA) for satellite communication applications. The device technology used relies on 0.25 ㎛ gate length gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (PHEMT) of wireless information networking (WIN) semiconductor foundry. The developed Ku-band PHEMT MMIC power amplifier has a small-signal gain of 22.2~23.1 dB and saturated output power of 34.8~35.4 dBm over the entire band of 13.75 to 14.5 GHz. Maximum saturated output power is a 35.4 dBm (3.47 W) at 13.75 GHz. Its power added efficiency (PAE) is 30.6~37.83% and the chip dimensions are 4.4 mm×1.9 mm. The developed 3 W PHEMT MMIC power amplifier is expected to be applied in a variety of Ku-band satellite communication applications.

Design of digitally controlled CMOS voltage mode DC-DC buck converter for high resolution duty ratio control (고해상도 듀티비 제어가 가능한 디지털 제어 방식의 CMOS 전압 모드 DC-DC 벅 변환기 설계)

  • Yoon, KwangSub;Lee, Jonghwan
    • Journal of IKEEE
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    • 제24권4호
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    • pp.1074-1080
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    • 2020
  • This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.