• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.359-363
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• 2005

유기 박막트랜지스터 (OTFT)를 제작하기 위하여 게이트 절연막으로서 PVP 계통의 유기막을 갖는 MIM(metal-insulator-metal)구조의 유기 절연층 소자를 제작하였다. 유기 절연층의 형은 ITO/Glass 기판위에 polyvinyl 계열의 PVP(poly-4-vinylphenol)를 용질로, PGMEA (propylene glycol monomethyl ether acetate)를 용매로 사용하여 co-polymer PVP를 제조하였다. 또한 열경화성 수지인 poly(melamine-co-formaldehyde)를 경화제로 사용하여 cross-linked PVP 절연막을 합성하였다. 유기 절연층의 전기적 특성은 co-polymer PVP 소자에 비해 cross-link 방식으로 제조된 소자에서 약 300 pA의 낮은 누설전류와 상대적으로 낮은 잡음전류의 특성을 나타내었다. 또한 cross-linked PVP 절연막에서 보다 양호한 표면형상 (거칠기)이 관찰되었으며 정전용량 값은 약 0.11${\~}$0.18 nF의 값을 나타내었다.

• 대한전자공학회논문지SD
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• 제40권12호
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• pp.1-9
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• 2003

본 논문에서는 cobalt interlayer와 TiN capping을 적용한 Ni-Silicide 구조를 제안하여 100 ㎜ CMOS 소자에 적용하고 소자 특성 연구를 하였다. Ni-Silicide의 취약한 열 안정성을 개선하기 위해 열 안정성이 우수한 Cobalt interlayer이용하여 silicide의 열화됨을 개선하였고 또한 silicide 계면의 uniformity를 향상하기 위해 TiN capping을 동시에 적용하였다. 100 ㎚ CMOS 소자에 제안한 Co/Ni/TiN 구조를 적용하여 700℃, 30분에서의 열처리 시에도 silicide의 낮은 면저항과 낮은 접합 누설 전류가 유지되었으며 100 ㎚이하 소자의 특성 변화도 거의 없음을 확인하였다. 따라서 제안한 Co/Ni/TiN 구조가 NiSi의 열 안정성을 개선시킴으로써 100 ㎚ 이하의 Nano CNOS 소자에 매우 적합한 Ni-Silicide 특성을 확보하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• 전기전자학회논문지
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• 제19권1호
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• pp.94-100
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• 2015

본 논문에서는 U-MOSFET 내부의 기생 body 다이오드(PN diode)를 쇼트키 body 다이오드(Schottky body diode)로 대체한 50V급 전력 U-MOSFET을 제안하였다. 쇼트키 다이오드는 PN 다이오드와 비교 시, 역 회복 손실(reverse recovery loss)을 감소시킬 수 있는 장점을 가지고 있다. 따라서 전력 MOSFET의 기생 body 다이오드를 쇼트키 body 다이오드를 대신함으로써 역 회복 손실을 최소화 할 수 있다. 제안된 쇼트키 body 다이오드(Schottky body diode) U-MOSFET(SU-MOS)를 conventional U-MOSFET(CU-MOS)와 전기적 특성을 비교한 결과, 전달(transfer) 및 출력(output)특성, 항복(breakdown)전압 등 정적(static) 특성의 변화 없이 감소된 역 회복 손실을 얻을 수 있었다. 즉, 쇼트키 다이오드의 폭(width)이 $0.2{\mu}m$, 쇼트키 장벽 높이(Schottky barrier height)가 0.8eV일 때 첨두 역전류(peak reverse current)는 21.09%, 역 회복 시간(reverse recovery time)은 7.68% 감소하였고, 성능지수(figure of merit(FOM))는 35% 향상되었다. 제안된 소자의 특성은 Synopsys사의 Sentaurus TCAD를 사용하여 분석되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1297-1300
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• 2008

A conventional linear accelerator system requires a flat-topped pulse with less than ${\pm}$ 0.5% ripple to meet the beam energy spread requirements and to improve pulse efficiency of RF systems. A pulse transformer is one of main determinants on the output pulse voltage shape. The pulse transformer was investigated and analyzed with the pulse response characteristics using a simplified equivalent circuit model. The damping factor ${\sigma}$ must be >0.86 to limit the overshoot to less than 0.5% during the flat-top phase. The low leakage inductance and distributed capacitance are often limiting factors to obtain a fast rise time. These parameters are largely controlled by the physical geometry and winding configuration of the transformer. A rise time can be improved by reducing the number of turns, but it produces larger pulse droop and requires a larger core size. By tradeoffs among these parameters, the high-voltage pulse transformer with a pulse width of 10 ${\mu}s$, a rise time of 0.84 ${\mu}s$, and a pulse droop of 2.9% has been designed and fabricated to drive a klystron which has an output voltage of 284 kV, 30-MW peak and 60-kW average RF output power. This paper describes design optimization of a high-voltage pulse transformer for high-power pulsed applications. The experimental results were analyzed and compared with the design. The design and optimal tuning parameter of the system was identified using the model simulation.

• Nutrition Research and Practice
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• 제6권4호
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• pp.366-374
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• 2012

In order to create a worker-friendly environment for institutional foodservice, facilities operating with a dry kitchen system have been recommended. This study was designed to compare the work safety and work environment of foodservice between wet and dry kitchen systems. Data were obtained using questionnaires with a target group of 303 staff at 57 foodservice operations. Dry kitchen facilities were constructed after 2006, which had a higher construction cost and more finishing floors with anti-slip tiles, and in which employees more wore non-slip footwear than wet kitchen (76.7%). The kitchen temperature and muscular pain were the most frequently reported employees' discomfort factors in the two systems, and, in the wet kitchen, "noise of kitchen" was also frequently reported as a discomfort. Dietitian and employees rated the less slippery and slip related incidents in dry kitchens than those of wet kitchen. Fryer area, ware-washing area, and plate waste table were the slippery areas and the causes were different between the functional areas. The risk for current leakage was rated significantly higher in wet kitchens by dietitians. In addition, the ware-washing area was found to be where employees felt the highest risk of electrical shock. Muscular pain (72.2%), arthritis (39.1%), hard-of-hearing (46.6%) and psychological stress (47.0%) were experienced by employees more than once a month, particularly in the wet kitchen. In conclusion, the dry kitchen system was found to be more efficient for food and work safety because of its superior design and well managed practices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.278.1-278.1
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• 2014

Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

• 한국진공학회지
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• 제11권3호
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• pp.135-140
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• 2002

본 논문에서는 p-type (100)Si, (100)MgO 그리고 MgO/si 기판 위에 RF Magnetron sputtering 법으로 $Ba_{0.5}Sr_{0.5}TiO_3$(BST)박막을 증착하였다. BST 박막 증착 후 RTA(Rapid Thermal Annealing)를 이용하여 $600^{\circ}C$에서 산소분위기로 1분간 고온 급속 열처리를 하였다. 증착된 BST박막의 결정화를 조사하기 위해 XRD(X-Ray Diffraction)측정을 한 결과 모든 기판에서 (110) $Ba_{0.5}Sr_{0.5}TiO_3$(의 주피크가 관찰되어졌고, 열처리 후 재결정화에 기인하여 피크 세기가 증가함을 관찰할 수 있었다. Al 전극을 이용한 커패시터 제작 후 측정한 C-V(Capacitance-Voltage) 특성에서 각각의 기판에서 측정된 커패시턴스 값으로 계산된 유전율은 120(bare Si), 305(Mgo/Si) 그리고 310(MgO)이었다. 누설 전류 특성에서는 0.3 MV/cm이내의 인가전계에서 1 $\mu\textrm{A/cm}^2$ 이하의 안정된 값을 보여주었다. 결론적으로 MgO 버퍼층을 이용한 기판이 BST 박막의 증착을 위한 기판으로써 효과적임을 알 수 있었다.

• 한국진공학회지
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• 제6권1호
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• pp.36-43
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• 1997

Pt/Ti/$SiO_2$/Si 기판상에 고주파 마그네트론 스퍼터링 방식으로 PZT 박막[두께:3000 $\AA$]을 증착하고 RTA방식으로 후속 열처리[열처리온도:$550^{\circ}C$~$650^{\circ}C$, 열처리 시간:10초~50 초]를 실시하여 직경 0.2mm소자의 FECAPs(ferroelectric capacitors)를 제작하였다. 제작된 커패시터의 유전상수($\varepsilon_r$)와 잔류분극($2P_r$)은 $650^{\circ}C$로 30초간 열처리한 시편에서 $\varepsilon_r$ (1kHz)=690, 2Pr(-5V~5V sweep)=22$\muC/\textrm{cm}^2$로 가장 높게 나타났으며 유전정접(tan $\delta$)과 누설전류(Jl)는 $600^{\circ}C$에서 30초간 열처리한 시편에서 $tan\delta(\ge10kHz)\le0.02, \; J_i(5V)=3\mu\textrm{A}/\textrm{cm}^2$로 가장 낮게 나타났다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.