• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.746-748
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• 2004

a-Si TFTs with field-effect mobility of 1.2 $cm^2$/V-s have been fabricated on plastic substrate. Pixel circuits on plastic for AMOLED were made with the same low-temperature fabrication process. The circuits compensate for $V_T$-shift, exhibit high output current, retain functionality and drive current level during long-time continuous operation.

• Journal of Industrial Technology
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• v.18
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• pp.165-172
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• 1998

In recent years, various power factor correction(PFC) circuits for the electronic ballast have been proposed. And these circuits have difference characteristics each other. We have researched several PFC circuits of them. And operational principles and characteristics of PFC circuits are compared by the cost and the electrical performance. Finally, we established the reference for the evaluation of PFC circuits with performance and the price.

• Journal of electromagnetic engineering and science
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• v.13 no.1
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• pp.54-61
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• 2013

An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.56-61
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• 2013

Modern integrated circuits (ICs) are becoming an integrated parts of analog, digital, and radio frequency (RF) circuits. Testing these RF circuits on a chip is an important task, not only for fabrication quality control but also for tuning RF circuit elements to fit multi-standard wireless systems. In this paper, RF test circuits suitable for embedded testing are introduced: RF power detectors, power control circuits, directional couplers, and six-port reflectometers. Various types of embedded RF power detectors are reviewed. The conventional approach and our approach for the RF power control circuits are compared. Also, embedded tunable active directional couplers are presented. Then, six-port reflectometers for embedded RF testing are introduced including a 77-GHz six-port reflectometer circuit in a 130 nm process. This circuit demonstrates successful calibrated reflection coefficient simulation results for 37 well distributed samples in a Smith chart. The details including the theory, calibration, circuit design techniques, and simulations of the 77-GHz six-port reflectometer are presented in this paper.

• Journal of Korean Vacuum Science & Technology
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• v.3 no.1
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• pp.66-73
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• 1999

In this paper, the design of one-chip FED system integrated with driving circuits in reported on the basis of MOSFET controlled FEA (MCFEA). To integrate a MOSFET with a FEA efficiently, a new fabrication process is proposed. It is confirmed that the MOSFET with threshold voltage of about 2volts controls the FEA emission current up to 20 ${\mu}$A by applying driving voltage of 15 volts, which is enough current level to utilize the MCFEA as a pixel for FED. The drain breakdown voltage of the MOSFET is measured to be 70 volts, which is also high enough for 60 volt operation of FED. The circuits for row and column driver are designed stressing on saving area, reducing malfunction probability and consuming low power to maximize the merit of on-chip driving circuits. Dynamic logic concept and bootstrap capacitors are used to meet these requirements. By integrating the driving circuit with FEA, the number of external I/O lines can be less than 20, irrespectively of the number of pixels.

• Journal of IKEEE
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• v.14 no.4
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• pp.283-290
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• 2010

This study is on the design of 10Gbps CMOS receiver circuits for fiber-optic communication. The receiver is made up of a photodiode, a transimpedance amplifier, a limiting amplifier, an equalizer, a clock and data recovery loop circuit, and a demultiplexer or demux with some auxiliary circuits including I/O circuits. Various wideband or high-speed circuit techniques are harnessed to realize a feasible, effective, and reliable receiver for a SONET fiber-optic standard, OC-192.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.151-154
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• 2020

Radiation noise due to EMI noise generated by the driving circuits of LED lighting devices in a medical imaging room was reduced by decreasing the noise source in the driving circuits and changing the number of corrections in EMI filters. Noise attenuation and filter changes enabled driving circuits that reduced the electromagnetic waves. Such circuits were efficiently designed by using capacitors and inverters in a given space. Therefore, the malfunction of radiation devices can be minimized by using EMI-reduction filter circuits, and reliable operation of medical devices can be expected by blocking electromagnetic waves.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.1
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• pp.13-23
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• 1983

This paper deals with the three-level PLA constructed by EXCLUSIVE-OR, AND, and OR. (abbreviated as EXANOR). Most PLA circuits have constraints on minimum chip area and minimal input lines. Thus, the reduction of PLA chip area is an important factor in design of logic circuits. In this paper, newly constructed architecture of PLA is proposed and then, its reduction effect is proved theoretically and some of selected examples are illustrated for designing three-level PLA circuits.