• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.27-35
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• 2004

Finite or Galois fields have been used in numerous applications such as error correcting codes, digital signal processing and cryptography. These applications often require exponetiation on GF(2$^{m}$ ) which is a very computationally intensive operation. Most of the existing methods implemented the exponetiation by iterative methods using repeated multiplications, which leads to much computational load, or needed much hardware cost because of their structural complexity in implementing. In this paper, we present an effective VLSI architecture for exponentiation on GF(2$^{m}$ ). This circuit computes the exponentiation by multiplying product terms, each of which corresponds to an exponent bit. Until now use of this type algorithm has been confined to a primitive element but we generalize it to any elements in GF(2$^{m}$ ).

• Journal of IKEEE
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• v.16 no.4
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• pp.310-315
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• 2012

This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. In thread management, there is no management hardware and implement with software instructions. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Land Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.

• Smart Media Journal
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• v.2 no.1
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• pp.17-26
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• 2013

Electronic bulletin boards, has been used as an effective tool in various information delivery. However, many electronic bulletin board as a one-way information passed by the interactivity is lacking. In this paper, the interaction of the information, while maintaining an electronic bulletin board that can be operated on a variety of platforms, the Android-based software and hardware for the design and implementation. The interaction of users of electronic bulletin boards, and information can be naturally-type content support Android framework was designed to allow Android APP. Android APP using the administrator also was designed automatic installation and FORUMS so that you can run. Naturally gather information, and all the people that interact through bulletin boards, so you can take advantage.

• Journal of Korea Multimedia Society
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• v.10 no.9
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• pp.1209-1219
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• 2007

It is difficult to run 3D graphics based application on the embedded system with hardware constraints. Therefore, such a system must have a systematic infrastructure which can process various operations with respect to 3D graphics through any graphic acceleration module. In this paper, we present a method to implement 3D graphics acceleration device driver on Tiny X platform which provide an open source graphics windowing environment. The proposed method is to initialize the driver step by step so that the direct rendering infrastructure can use it properly. Moreover, we evaluated overall 3D graphics performance of an implemented driver through a simple but effective benchmark program.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.645-648
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• 2012

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 SAO(Sample Adaptive Offset)의 하드웨어 구조 설계에 대해 기술한다. SAO는 양자화 등의 손실 압축에 의해 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC의 최대 블록 크기인 $64{\times}64$ 단위를 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 SAO 하드웨어 구조는 $8{\times}8$ 단위를 처리하는 연산기로 구성하여 하드웨어 면적을 최소화하였고, 내부레지스터를 이용하여 $64{\times}64$ 블록 크기를 지원한다. 또한 기존 SAO의 top-down 블록분할 구조에서 down-top 블록분할 구조로 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 $0.18{\mu}m$ 셀 라이브러리로 합성한 결과 동작 주파수는 250MHz, 전체 게이트 수는 45.4k 이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1506-1509
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• 2013

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 in-loop filter의 하드웨어 구조 설계에 대해 기술한다. in-loop filter는 deblocking filter와 SAO로 구성되며, 블록 단위 영상 압축 및 양자화 등에서 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC는 $64{\times}64$ 블록 크기까지 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 in-loop filter의 deblocking filter 모듈과 SAO 모듈은 최소 연산 단위인 $8{\times}8$ 블록 연산기로 구성하여 하드웨어 면적을 최소화하였다. 또한 SAO에서는 $8{\times}8$ 블록의 연산 결과를 내부레지스터에 저장하는 구조로 $64{\times}64$ 블록 크기를 지원하도록 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 180nm 셀 라이브러리로 합성한 결과 동작 주파수는 270MHz이고, 전체 게이트 수는 48.9k이다.

• Archives of design research
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• no.18
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• pp.25-34
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• 1996

Industrial design development methods and processes have changed in accordance with Industrial Information Age. These days, problems are created by existing methods and evaluation of design value , all problems concerned with time and finances sitaution have been made a subject of discussion. Development of design processes have been changed by the development of problem recognition and solving tools, and dpsign tpchnulugy havp hppn replaced by computer technology,Thus. software design processes linking thoughtware to hardware are used in the solution of design problems with many parts. In this study, 3D Modeling samples are presented, 3D Modeling can realise ' Ideas' to '3Dimentional Virtual Ohjects'. These effect and value are anle to decisively influence the process of design problem conference-ebealuation-solution.Proxesses of actual modeling and rendering are made as follows. By compusition of simple 20 drawings and shaping them into 30 objects, 30 solid models can be made. To prssent effectivley, we can make a sample model by varying camera views,light sourses,materials and colours etc. This sample is evaluated by various cumposition, methods and PERT(Program Evaluation and Review Technique). This cuncrete sample (tentative plan)is changed within the CAD SYSTEM by design evaluation, and then converted to flowchart of mass productive conception through refined data. So, that tentative plan can be conformed to design desire actuillly, to the utmost degree. Finally, this design process can be proposed as il new method in cuntrast with current methods. The aim of this study is to suggest effective evaluation methods of design outcome among many evaluating elements.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.305-316
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• 2006

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

• The Journal of the Convergence on Culture Technology
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• v.8 no.6
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• pp.79-88
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• 2022

The purpose of this study was to explore which factors should be considered mainly in operating hybrid learning in which offline and synchronous online environments are integrated in elementary education. Using qualitative data through interview and so on for 8 elementary school teachers with experience in operating hybrid learning, major consideration factors were identified. Before class, it is necessary to increase the level of understanding through concrete guidance or education for what the characteristics of hybrid learning are. The redesign of the environment including hardware and software technology is considered because the foundation was not established properly so that effective operation was difficult. In particular, based on the simultaneity and interactivity between the environments, activities which learners can connect and participate in the two environments should be considered. Further, design strategies to guide the operation of teaching and learning will be developed.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.