• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.290-295
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• 2005

The incremental encoder has been mostly used to measure the speed and position of the motor. As the output signals of encoder are high frequency digital signals, they have much influence on radiation noises due to switching of the power semiconductor circuits. It is so difficult to suppress the noises with the conventional LPF. In this paper, the hardware digital filter for suppressing noises in the output signals of the encoder signals is developed. As both the clock frequency and counter in the digital filter for encoder are easily adjusted according to the kinds of noises, any noises in the encoder can be entirely eliminated. The performance of the digital filter has been verified by simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7A
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• pp.632-638
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• 2010

In this paper, we propose a fixed-complexity sphere encoder (FSE) for multi-user MIMO (MU-MIMO) systems. The Proposed FSE accomplishes a scalable tradeoff between performance and complexity. Also, because it has a parallel tree-search structure, the proposed encoder can be easily pipelined, leading to a tremendous reduction in the precoding latency. The complexity of the proposed encoder is also analyzed, and we propose two techniques that reduce it. Simulation and analytical results demonstrate that in a $4\times4$ MU-MIMO system, the complexity of the proposed FSE is 16% that of the conventional QRD-M encoder (QRDM-E). Also, the encoding throughput of the proposed endoder is 7.5 times that of the QRDM-E with tolerable degradation in the BER performance, while achieving the optimum diversity order.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.603-608
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• 2016

Encoding means converting or processing form or format of information into the other forms to standardize, secure, improve processing speed, store saving spaces and etc. Also, Encoding is converting the information so as to do transmit other form on the sender's information to the receiver in Information-Communication. The device that is conducting the processing is called the encoder. In this dissertation, proposes an encoder of the most basic 4-to-2 encoder. proposed encoder consists of two OR-gate and the proposed structure designs and optimize the spacing of the cell for the purpose of minimizing noise between wiring. Through QCADesigner conducts simulation of the proposed encoder and analyzes the results confirm the effectiveness.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.9-16
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• 1997

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.445-452
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• 2010

In this paper, an attempt has been made to design the controller applicable for H.264 level3 encoder of baseline profile on full hardware basis. The designed controller module first stores the images supplied from CMOS Image Sensor(CIS) at main memory, and then reads or stores the image data in macroblock unit according to encoder operation. The timing cycle of the DMA controller required to process a macroblock is 478 cycles. In order to verify the our design, reference-C encoder, which is compatible to JM 9.4, is developed and the designed controller is verified by using the test vector generated from the reference C code. The number of cycle in the designed DMA controller is reduced by 40% compared with the cycle of using Xilinx MIG.

• Journal of the Korean Society for Precision Engineering
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• v.33 no.12
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• pp.1007-1013
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• 2016

This paper presents the development of a magneto-optical encoder for higher precision and smaller size. In general, optical encoders can have very high precision based on the position information of the slate, while their sizes tend to be larger due to the presence of complex and large components, such as an optical module. In contrast, magnetic encoders have exactly the opposite characteristics, i.e., small size and low precision. In order to achieve encoder features encompassing the advantages of both optical and magnetic encoders, i.e., high precision and small size, we designed a magneto-optical encoder and developed a method to detect absolute position, by compensating for the error of the hall sensor using the linear table compensation method. The performance of the magneto-optical encoder was evaluated through an experimental testbed.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.11a
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• pp.47-50
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• 2022

In this paper, we proposed a method for Video-based point cloud compression reference software TMC2 encoder with an option for empty partitions in point cloud encoding. This encoder option allows tile initialization and process for an empty partition. The proposed method provides the TMC2 encoder the robustness to process dynamic point clouds.