• Title/Summary/Keyword: ENCODER

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The Study on the Composition of the Encoder for Driving the High Speed Spindle Motor (고속 스핀들 전동기 구동을 위한 자기식 엔코더 구성에 관한 연구)

  • Choi Cheol;Kim Cheol-U;Lee Sang-Hun
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.54 no.5
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    • pp.253-259
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    • 2005
  • Magnetic encoder with relatively low pulse per rotation is generally used for detecting speed of the high-speed rotating machine. It is due to the fact of the mechanical problems of vibration and bearing stiffness and also the limit of maximum output pulse of the mounted encoder. The magnetic encoder is divided into two types, that is, toothed gear-wheel method and magnetic wheel method according to the shape of the rotation disk. In case of detecting speed by the tooth gear-wheel, the encoder itself can be acted as the additional inertia where the number of tooth determining the output pulse and the width of the wheel detecting the change of the magnetic flux density are relatively enough large considering the volume of the rotating machine. While the magnetic wheel method has the limit of the magnetizing number of the ring magnet, there is relatively few, if nv, the influence of inertia on the machine. In this paper, it is proposed a simple magnetic wheel encoder suited for the high speed rotating machine and the method of signal processing and the output characteristics are examined through the V/F operation of max 48,000(rpm) and 2.4(KW) spindle motor.

Design and Development of a Novel High Resolution Absolute Rotary Encoder System Based on Affine n-digit N-ary Gray Code

  • Paul, Sarbajit;Chang, Junghwan
    • Journal of Electrical Engineering and Technology
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    • v.13 no.2
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    • pp.943-952
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    • 2018
  • This paper presents a new type of absolute rotary encoder system based on the affine n-digit N-ary gray code. A brief comparison of the existing encoder systems is carried out in terms of resolution, encoding and decoding principles and number of sensor heads needed. Using the proposed method, two different types of encoder disks are designed, namely, color-coded disk and grayscale coded disk. The designed coded disk pattern is used to manufacture 3 digit 3 ary and 2 digit 5 ary grayscale coded disks respectively. The manufactured disk is used with the light emitter and photodetector assembly to design the entire encode system. Experimental analysis is done on the designed prototype with LabVIEW platform for data acquisition. A comparison of the designed system is done with the traditional binary gray code encoder system in terms of resolution, disk diameter, number of tracks and data acquisition system. The resolution of the manufactured system is 3 times higher than the conventional system. Also, for a 5 digit 5 ary coded encoder system, a resolution approximately 100 times better than the conventional binary system can be achieved. In general, the proposed encoder system gives $(N/2)^n$ times better resolution compared with the traditional gray coded disk. The miniaturization in diameter of the coded disk can be achieved compared to the conventional binary systems.

A Study on Classification of Variant Malware Family Based on ResNet-Variational AutoEncoder (ResNet-Variational AutoEncoder기반 변종 악성코드 패밀리 분류 연구)

  • Lee, Young-jeon;Han, Myung-Mook
    • Journal of Internet Computing and Services
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    • v.22 no.2
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    • pp.1-9
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    • 2021
  • Traditionally, most malicious codes have been analyzed using feature information extracted by domain experts. However, this feature-based analysis method depends on the analyst's capabilities and has limitations in detecting variant malicious codes that have modified existing malicious codes. In this study, we propose a ResNet-Variational AutoEncder-based variant malware classification method that can classify a family of variant malware without domain expert intervention. The Variational AutoEncoder network has the characteristics of creating new data within a normal distribution and understanding the characteristics of the data well in the learning process of training data provided as input values. In this study, important features of malicious code could be extracted by extracting latent variables in the learning process of Variational AutoEncoder. In addition, transfer learning was performed to better learn the characteristics of the training data and increase the efficiency of learning. The learning parameters of the ResNet-152 model pre-trained with the ImageNet Dataset were transferred to the learning parameters of the Encoder Network. The ResNet-Variational AutoEncoder that performed transfer learning showed higher performance than the existing Variational AutoEncoder and provided learning efficiency. Meanwhile, an ensemble model, Stacking Classifier, was used as a method for classifying variant malicious codes. As a result of learning the Stacking Classifier based on the characteristic data of the variant malware extracted by the Encoder Network of the ResNet-VAE model, an accuracy of 98.66% and an F1-Score of 98.68 were obtained.

Design of the Successive Selection Encoder by the Logical Effort for High Flash Speed ADC's (고속 플래시 AD 변환기를 위한 Successive Selection Encoder의 Logical Effort에 의한 설계)

  • Lee Kijun;Choi Kyusun;Kim Byung-soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.37-44
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    • 2005
  • In this paper, a new type of the TC-to-BC encoder for high speed flash ADC's, called the Successive Selection Encoder (SSE), is proposed. In contrast to the conventional fat tree encoder based on OR operations, the W- outputs, in the new design, are obtained directly from TC inputs through simple MUX operations. The detailed structure of the SSE has been determined systematically by the method of the logical effort and the simulation oil Hynix 0.25um process. The theoretical and experimental results show that (1) it is not required to generate one-out-of-n signals, (2) the number of gates is reduced by the factor of 1/3, and (3) the speed is improved more than 2-times, compared to the fat tree encoder. It is speculated that the SSE proposed in this study is an effective solution for bottleneck problems in high speed ADCs.

Double Encoder-Decoder Model for Improving the Accuracy of the Electricity Consumption Prediction in Manufacturing (제조업 전력량 예측 정확성 향상을 위한 Double Encoder-Decoder 모델)

  • Cho, Yeongchang;Go, Byung Gill;Sung, Jong Hoon;Cho, Yeong Sik
    • KIPS Transactions on Software and Data Engineering
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    • v.9 no.12
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    • pp.419-430
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    • 2020
  • This paper investigated methods to improve the forecasting accuracy of the electricity consumption prediction model. Currently, the demand for electricity has continuously been rising more than ever. Since the industrial sector uses more electricity than any other sectors, the importance of a more precise forecasting model for manufacturing sites has been highlighted to lower the excess energy production. We propose a double encoder-decoder model, which uses two separate encoders and one decoder, in order to adapt both long-term and short-term data for better forecasts. We evaluated our proposed model on our electricity power consumption dataset, which was collected in a manufacturing site of Sehong from January 1st, 2019 to June 30th, 2019 with 1 minute time interval. From the experiment, the double encoder-decoder model marked about 10% reduction in mean absolute error percentage compared to a conventional encoder-decoder model. This result indicates that the proposed model forecasts electricity consumption more accurately on manufacturing sites compared to an encoder-decoder model.

Development of an MPEG-2 Encoder System for Satellite and Terrestrial Broadcast (위성 및 지상파 방송용 MPEG-2 인코더 시스템 개발)

  • 이진환;안치득;정주홍;장현식;양진영
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 1999.11b
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    • pp.81-84
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    • 1999
  • The paper describes MPEG-2 encoder system developed by ETRI. The encoder system consists of video encoder, audio encoder and program multiplexer. The system can be used as an SDTV encoder as well as a sub-picture encoding module of an HDTV encoder. In order to reduce the hardware size and increase the system reliability, most parts of the MPEG-2 encoding algorithm are implemented with ASIC chips except the rate control part. The developed system is compliant with MPEG-2 and ATSC.

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Development of an MPEG-4 AAC encoder of low implementation complexity (낮은 연산 부담을 갖는 MPEG-4 AAC 인코더 개발에 관한 연구)

  • 김병일;김동환;장태규;장흥엽
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2467-2470
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    • 2003
  • This paper presents a new structure of MPEG-4 AAC encoder. The proposed encoder directly shapes quantization noise distribution according to the energy distribution curve and thereafter performs adjustment of the offset level of the noise distribution to meet the given bit rate. The direct noise shaping and the bit rate matching scheme of the proposed encoder algorithm significantly alleviate the problem of conventional encoder's processing burden related with the employment of the precise psychoacoustic model and iteration intensive quantizer. The encoder algorithm is implemented on ARM processor with fixed-feint arithmetic operations. The audio quality of the implemented system is observed comparable to those of commercially available encoders, white the complexity of the implementation is drastically reduced in comparison to the conventional encoder systems.

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A design of Direct Memory Access For H.264 Encoder (H.264 Encoder용 Direct Memory Access (DMA) 설계)

  • Jung, Il-Sub;Suh, Ki-Bum
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.91-94
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    • 2008
  • The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.

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New Encoder/Decoder with Wavelength/Time 2-D Codes for Optical CDMA Network (광 부호 분할 다중접속 네트워크를 위한 파장/시간 2차원 코드의 새로운 부호기/복호기)

  • Hwang, Hu-Mor
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.5
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    • pp.1035-1040
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    • 2009
  • We propose a new encoder/decoders based on an tune able wavelength converter(TWC) and an arrayed waveguide grating(AWG) router for large capacity optical CDMA networks. The proposed encoder/decoder treats codewords of wavelength/time 2-D code simultaneously using the dynamic code allocation property of the TWC and the cyclic property of the AWG router, and multiple subscribers can share the encoder/decoder in networks. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using two wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC) and the generalized multi-wavelength Reed-Solomon code(GMWRSC). Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

Comparing the Performances of Intent Classifications by Encoder Layer (Encoder Layer를 이용한 의도 분류 성능 비교)

  • Ahn, Hyeok-Ju;Kim, Hye-Young
    • Annual Conference on Human and Language Technology
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    • 2021.10a
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    • pp.410-413
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    • 2021
  • 본 논문에서는 분류 모델의 주류로 사용되고 있는 Encoder 기반 사전학습 모델(BERT, ALBERT, ELECTRA)의 내부 Encoder Layer가 하부 Layer에서는 Syntactic한 분석을 진행하고 상부 Layer로 갈수록 Semantic 한 분석을 진행하는 점, Layer가 구성됨에 따라 Semantic 정보가 Syntactic 정보를 개선해 나간다 점에 기반한 기존 연구 결과를 바탕으로 Encoder Layer를 구성함에 따라 어떻게 성능이 변화하는지 측정한다. 그리고 의도 분류를 위한 학습 데이터 셋도 분류하고자 하는 성격에 따라 Syntactic한 구성과 Semantic한 구성을 보인다는 점에 착안하여 ALBERT 및 ELECTRA를 이용한 의도 분류 모델을 구축하고 각 데이터 셋에 맞는 최적의 Encoder Layer 구성을 가지는 모델을 비교한 결과, 두 데이터 셋 간에 다른 Layer 구성을 보이는 점과 기존 모델보다 성능이 향상됨을 확인하였다.

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