• Korean Journal of Optics and Photonics
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• v.12 no.2
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• pp.103-108
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• 2001

In this paper, we designed and made the scanned point detecting system for 3-dimensional measurement of the light emitted from plasma display panel (PDP) , and we measured and analyzed 3-dimensional light emitted from a real PDP by using this scanned point detecting system. The scanned point detecting system has a point detector with a pinhole. The light emitted from the source at the in-focus position can pass through the pinhole and be collected by detector. The light from other sources at outof-focus positions is focused at points in front of or behind the pinhole, and thus it is intercepted by the pinhole. Therefore, we can detect light information from a particular point of a PDP cell of 3-dimensional structure. We know the electric field distribution inside the PDP cell from the 3-dimensionallight intensity distribution measured by using the scanned point detecting system. As the Z axial measurement increases, the intensity of light detected increases and intensity of light detected on the inside edge of the ITa electrode is larger than outside edge of the ITa eletrode and gap of the ITa electrodes. Also, as the measurement point moves from one barrier rib to another, the detected light is weaker near to the barrier ribs than at the center between the barrier ribs. The emitted light is concentrated at the center between barrier ribs. ribs.

• Transactions on Semiconductor Engineering
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• v.2 no.1
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• pp.17-20
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• 2024

This paper presents a novel lightweight object detection model tailored for low-powered edge devices, addressing the limitations of traditional resource-intensive computer vision models. Our proposed detector, inspired by the Single Shot Detector (SSD), employs a compact yet robust network design. Crucially, it integrates an 'enhancer block' that significantly boosts its efficiency in detecting smaller objects. The model comprises two primary components: the Light_Block for efficient feature extraction using Depth-wise and Pointwise Convolution layers, and the Enhancer_Block for enhanced detection of tiny objects. Trained from scratch on the Udacity Annotated Dataset with image dimensions of 300x480, our model eschews the need for pre-trained classification weights. Weighing only 5.5MB with approximately 0.43M parameters, our detector achieved a mean average precision (mAP) of 27.7% and processed at 140 FPS, outperforming conventional models in both precision and efficiency. This research underscores the potential of lightweight designs in advancing object detection for edge devices without compromising accuracy.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.449-450
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• 2007

오래 전 부터 영상처리와 컴퓨터 비전은 많은 분야에 응용되고 발전 되어 왔다. 그러한 기술 중에 최근 각광 받고 있는 그래프 짓(Graph cut) 알고리즘은 에너지함수를 최소화 하는 가장 강력한 최적화 기법중 하나이다. 그리고 일반적으로 Sobel, Prewitt, Roberts, Canny 에지(edge) 검출기 등은 영상처리에서 영상상의 에지를 검출하기 위해 이미 널리 사용되고 발전되어 온 기술이다. 물체에서의 윤곽만 검출하기 위해서는 우리가 원하지 않는 영상 위의 에지도 검출되기 때문에 예지 검출기만으로는 물체의 윤곽만을 검출하는 것은 불가능하다. 우리는 물체의 윤곽만 검출하기를 원하기 때문에 그래프 컷과 에지 검출기의 알고리즘을 결합하면 이러한 문제를 해결 할 수 있다는 것을 제안한다. 이 논문에서는 그래프 컷 알고리즘과 에지 검출기에 관해 간략하게 기술하고 그 결과를 보일 것이다.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.57-66
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• 2011

In this paper, it is proposed for algorithm to detect human efficiently using a edge symmetry and gradient directional characteristics in realtime by the feature extraction in a single input image. Proposed algorithm is composed of three stages, preprocessing, region partition of human candidates, verification of candidate regions. Here, preprocessing stage is strong the image regardless of the intensity and brightness of surrounding environment, also detects a contour with characteristics of human as considering the shape features size and the condition of human for characteristic of human. And stage for region partition of human candidates has separated the region with edge symmetry for human and size in the detected contour, also divided 1st candidates region with applying the adaboost algorithm. Finally, the candidate region verification stage makes excellent the performance for the false detection by verifying the candidate region using feature vector of a gradient for divided local area and classifier. The results of the simulations, which is applying the proposed algorithm, the processing speed of the proposed algorithms is improved approximately 1.7 times, also, the FNR(False Negative Rate) is confirmed to be better 3% than the conventional algorithm which is a single structure algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.136-139
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• 2012

본 논문에서는 에지 검출기를 이용하여 선택적 디인터레이싱 방법을 제안한다. 제안하는 알고리즘은 LA 방법, M-ELA 방법 그리고 DOI 방법을 기본 방법으로 사용하였다. 제안한 방법에서 크게 3단계로 나눠진다. 먼저 비월주사 영상을 M-ELA 방법을 이용하여 에지의 방향을 예측한 후, 잃어버린 화소 값을 보간한다. 여기서 더 정밀한 에지를 검출하기 위해 소벨 연산을 사용하여 에지 방향에 따라 LA 방법, M-ELA 방법 그리고 DOI 방법을 선택적으로 보간하는 디인터레이싱 방법을 제안한다. 다양한 실험 영상에 대해 객관적 및 주관적 평가를 통해 제안한 알고리즘이 기존의 디인터레이싱 알고리즘보다 우수한 성능을 확인한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.355-362
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• 2009

A new intra field deinterlacing algorithm with edge map in the image block is introduced. Conventional deinterlacing methods usually employ edge-based line average algorithm within pixel-by-pixel approach. However, it is sensitive to variation of intensity. To reduce this shortcoming, we proposed edge direction vector computed by edge map, and also its interpolation technique. We first introduce an edge direction vector, which is computed by Sobel mask, so that finer resolution of the edge direction can be acquired. The proposed edge direction vector oriented deinterlacer operates by identifying small pixel variations in five orientations, while weighted averaging to estimate missing pixel. According to the edge direction of the direction vector, we calculate weights on each edge direction. These weight values multiplied by the candidate deinterlaced pixels in order to successively build approximations of the deinterlaced sequence.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.3
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• pp.37-46
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• 2012

In RADAR and SONAR detection systems, noise environment can be classified into homogeneous and heterogeneous environment. Especially heterogeneous environments are modelled as target masking and clutter edge. Since the variability-index (VI) CFAR, a composed CFAR algorithm, dynamically selects one of the mean-level algorithms based on the VI and the MR (mean ratio) test, it is robust to various environments. However, the VI CFAR still suffers from lowered detection probabilities in heterogeneous environments. To overcome these problems, we propose an improved VI CFAR processor where TM (trimmed mean) CFAR and a sub-windowing technique are introduced to minimize the degradation of the detection probabilities appeared in heterogeneous environments. Computer simulation results show that the proposed method has the better performance in terms of detection probability and false alarm probability compared to the VI CFAR and single CFAR algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.587-593
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• 2010

In this paper we design an irregular low-density parity-check (LDPC) code for multiple-input multiple-output (MIMO) system, using a simple extrinsic information transfer (EXIT) chart method. The MIMO systems considered are optimal maximum a posteriori probability (MAP) detector. The MIMO detector and the LDPC decoder exchange soft information and form a turbo iterative receiver. The EXIT charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the MIMO detector. It is shown that the performance of the designed LDPC code is better than that of conventional LDPC code which was optimized for either the Additive White Gaussian Noise (AWGN) channel or the MIMO channel.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise