• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• Proceedings of the KIEE Conference
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• 2001.11b
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• pp.146-148
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• 2001

This paper discusses the optimal sizes of BESS. The goal must be optimized electricity charge of the customers-side with choosing the time-of-use rates. Therefore the cost is minimized by BESS installed the customers-side. Feasible ROR that means the ratio of capital costs to economic effect owned the optimal BESS sizes is determined the suitable domestic condition based on the battery cost and power converter system cost. Payback period times can be presented by BESS through the ROR. Multi-Pass Dynamic Programming(MPDP) algorithm is applied to the customer for the optimal sizes determination in this paper. It is to solve the optimal solution under the constraints. To investigate the efficiencies of the constraints, it is applied the typical load curve to the high-voltage customer owned Time-Of-Use(TOU) whether BESS is installed or not. Well, The result is obtained that feasible BESS sizes can be achieved the suitable customers-side of meter through the ROR.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.12
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• pp.210-216
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• 2009

Distributed Generation (DG) is predicted to play a important role in electric power system in the near future. insertion of DG system into existing distribution network has great impact on real-time system operation and planning. It is widely accepted that micro turbine generation (MTG) systems are currently attracting lot of attention to meet customers need in the distributed power generation market. In order to investigate the performance of MT generation systems, their efficient modeling is required. This paper presents the modeling and simulation of a MT generation system suitable for stand-alone operation. The system comprises of a permanent magnet synchronous generator driven by a MT. A brief description of the overall system is given, and mathematical models for the MT and permanent magnet synchronous generator are presented. Also, the use of power electronics in conditioning the power output of the generating system is demonstrated. Simulation studies with MATLAB/Simulink have been carried out in stand-alone operation mode of a DG system.

• Journal of Power Electronics
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• v.15 no.2
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• pp.299-308
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• 2015

This study proposes four novel pulse width modulation (PWM) shoot-through control methods for impedance source (IS) galvanically isolated DC-DC converters. These methods are derived from a PWM control method with shifted shoot-through introduced by the authors in 2012. In contrast to the baseline solution, where the shoot-through states are generated by the simultaneous conduction of all transistors in the inverter bridge, our new approach is based on the shoot-through generation by one inverter leg. The idea is to increase the number of soft-switched transients and, therefore, decrease the dynamic losses of the front-end inverter. All the proposed approaches are experimentally verified through an insulated-gate bipolar transistor-based IS DC-DC converter. Conclusions are drawn in accordance with the results of the switching loss analysis.

• Journal of Power Electronics
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• v.11 no.3
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• pp.271-278
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• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.295-296
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• 1998

With xeroradiography appearance, DR (Digital Radiography) system have been studying for X-ray detection using photoreceptor. Also detection method for receptor charge change have been developing variably. We use photoreceptor material of a-Se(Amorphous Selenium) with high DQE, high SNR(Signal to Noise Ratio) and high transformation efficiency of X-ray signals into electrical signals. After a-Se receptor is uniformly charged by using Arc discharge, X-ray is exposed. Then a-Se receptor produce subtle charge variation and MOSFET detect charge variations. The detected signal pass A/D converter and signal processing by PC. As results, the initial voltage is 8V. It has wide dynamic range needed digital radiography system. In this study, we obtained data with changing kVp(tube potential voltage) and fixed 8mAs(tube current by exposure time) in X-ray system. However MOSFET detector for X-ray signal is not tested X-ray mAs variations. But if MOSFET detector is tested X-ray mAs variation and exactly calibrated multichannel is made and noise-reduction is done, suitable DR system readout method will be done.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1625-1636
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• 2017

A power electronic transformer (PET) based on the cascaded H-bridge (CHB) and the isolated bidirectional DC/DC converter (IBDC) is capable of accommodating a large scale battery energy storage system (BESS) in the medium-voltage grid, and is referred to as a power electronic transformer based battery energy storage system (PET-BESS). This paper investigates the PET-BESS and proposes a coordinative control strategy for it. In the proposed method, the CHB controls the power flow and the battery state-of-charge (SOC) balancing, while the IBDC maintains the dc-link voltages with feedforward implementation of the power reference and the switch status of the CHB. State-feedback and linear quadratic Riccati (LQR) methods have been adopted in the CHB to control the grid current, active power and reactive power. A hybrid PWM modulating method is utilized to achieve SOC balancing, where battery SOC sorting is involved. The feedforward path of the power reference and the CHB switch status substantially reduces the dc-link voltage fluctuations under dynamic power variations. The effectiveness of the proposed control has been verified both by simulation and experimental results. The performance of the PET-BESS under bidirectional power flow has been improved, and the battery SOC values have been adjusted to converge.

• Journal of Power Electronics
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• v.14 no.3
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• pp.444-457
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• 2014

This paper presents the design and realization of a digital PV simulator with a Push-Pull Forward (PPF) circuit based on the principle of modular hardware and configurable software. A PPF circuit is chosen as the main circuit to restrain the magnetic biasing of the core for a DC-DC converter and to reduce the spike of the turn-off voltage across every switch. Control and I/O interface based on a personal computer (PC) and multifunction data acquisition card, can conveniently achieve the data acquisition and configuration of the control algorithm and interface due to the abundant software resources of computers. In addition, the control program developed in Matlab/Simulink can conveniently construct and adjust both the models and parameters. It can also run in real-time under the external mode of Simulink by loading the modules of the Real-Time Windows Target. The mathematic models of the Push-Pull Forward circuit and the digital PV simulator are established in this paper by the state-space averaging method. The pole-zero cancellation technique is employed and then its controller parameters are systematically designed based on the performance analysis of the root loci of the closed current loop with $k_i$ and $R_L$ as variables. A fuzzy PI controller based on the Takagi-Sugeno fuzzy model is applied to regulate the controller parameters self-adaptively according to the change of $R_L$ and the operating point of the PV simulator to match the controller parameters with $R_L$. The stationary and dynamic performances of the PV simulator are tested by experiments, and the experimental results show that the PV simulator has the merits of a wide effective working range, high steady-state accuracy and good dynamic performances.