• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.9-16
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• 2016

Since most of devices in the IEEE 802.15.4 LR-WPAN are expected to operate on batteries, they must be designed to consume energy in a very conservative way. Two energy conservation algorithms are proposed for the LR-WPAN: DDC (Dynamic Duty Cycle) and DBT (Dynamic Beacon Tracking). The DDC algorithm adjusts duty cycle dynamically depending on channel conditions. The DBT algorithm switches beacon tracking mode on and off adaptively depending on traffic conditions. Combining the two algorithms reduces energy consumption more efficiently for a wide range of input loads, while maintaining frame delivery ratio and average delay at satisfactory levels.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• Journal of Information Processing Systems
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• v.13 no.5
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• pp.1320-1330
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• 2017

Wireless sensor networks for forest monitoring are typically deployed in fields in which manual intervention cannot be easily accessed. An interesting approach to extending the lifetime of sensor nodes is the use of energy harvested from the environment. Design constraints are application-dependent and based on the monitored environment in which the energy harvesting takes place. To reduce energy consumption, we designed a power management scheme that combines dynamic duty cycle scheduling at the network layer to plan node duty time. The dynamic duty cycle scheduling is realized based on a tier structure in which the network is concentrically organized around the sink node. In addition, the multi-paths preserved in the tier structure can be used to deliver residual packets when a path failure occurs. Experimental results show that the proposed method has a better performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.193-198
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• 2016

For environmental monitoring and risk identification of industrial plants, several monitoring systems using Wireless Sensor Networks (WSNs) have been developed. In this paper, we propose a dynamic duty cycle adjustment mechanism for reduced latency in industrial plants. The proposed method adjusts the duty cycle among predefined risk groups depending on the urgency of sensed data values. To demonstrate its efficacy, we analyze the expected transmission latency model and then discuss the characteristics in detail. We show that the proposed dynamic duty cycle mechanism is a more effective than a periodic mechanism by analyzing the expected latency of them in industrial plants where there are various types of sensory data with different levels of reliability.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.45-55
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• 2012

The energy efficiency is extremely significant in Wireless Sensor Networks (WSN) which deliver the data sensed in the sensor field, using wireless communications. Under the characteristics of WSN, many MAC protocols employ the Duty Cycle mechanism which continuously operates Wakeup and Sleep periods, for the energy efficiency. However, constant Wakeup period in general Duty Cycle incurs the limited performance of the energy efficiency and the receiving ratio. For addressing this, we design and propose a new scheme called Variable Wakeup Period, considering local traffic conditions. Our scheme enhances receiving ratio by increasing Wakeup period under the high traffic condition, and makes high energy efficiency by decreasing Wakeup period under the otherwise condition. In addition, we evaluate the performance of our scheme by performing the simulation, which experiments the previous synchronous and asynchronous MAC protocols, and which also experiments the same protocols with the proposed scheme, for comparative evaluations.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.470-475
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• 2002

Instantaneous following PWM control technique is pulsed nonlinear dynamic control method. This new control technique using analog integrator is proposed to control the duty ratio D of do-dc converter. In this control method, the duty ratio of a switch is exactly equal In or proportional to the control reference in the steady state or in a transient. Proposed control method compensates power source perturbation in one switching cycle, and the average value of the dynamic reference in one switching cycle. There is no steady state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with buck converter have demonstrated the robustness of the control method and verified theoretical prediction. The control method is very general and applicable to all type PWM

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.378-381
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• 2002

Instantaneous following PWM control technique is pulsed nonlinear dynamic control method. This new control technique using analog integrator is proposed to control the duty ratio D of DC-DC converter. In this control method, the duty ratio of a switch is exactly equal to or proportional to the control reference in the steady state or in a transient. Proposed control method compensates power source perturbation in one switching cycle, and the average value of the dynamic reference in one switching cycle. There is no steady state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with buck converter have demonstrated the robustness of the control method and verified theoretical prediction. The control method is very general and applicable to all type PWM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.103-105
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• 2002

Instantaneous following PWM control technique is pulsed nonlinear dynamic control method. This new control technique using analog integrator is proposed to control the duty ratio D of Cuk converter. In this control method, the duty ratio of a switch is exactly equal to or proportional to the control reference in the steady state or in a transient. Proposed control method compensates power source perturbation in one switching cycle, and the average value of the dynamic reference in one switching cycle. There is no steady state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with Cuk converter have demonstrated the robustness of the control method and verified theoretical prediction. The control method is very general and applicable to all type PWM.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.