• 한국전문물리치료학회지
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• 제12권2호
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• pp.90-97
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• 2005

By measuring changes in blood lactate and plasma enzyme (CPK, GOT, GPT) with electrical stimulation applied at two duty cycles, this study is intended to look into which type of duty cycle may have more effects on blood lactate and plasma enzyme constituents through animal experiment so as to determine any duty cycle appropriate for electrical treatment. In this study, electrical stimulation was applied to total 20 Korean house rabbits (weight: 3~3.5 kg) by means of an electrical therapeutic apparatus called TS6000 (made in Netherlands) at duty cycle of 50% and 20% respectively for 30 minutes. Here, 5 cc of blood was collected from their carotid artery before stimulation and in 30 minutes after stimulation respectively to carry out biochemical experiment and analysis. As determined through the above experiment, blood lactate rate was increased to 333.07% at 50% duty cycle after experiment and 185.71% at 20% duty cycle after experiment respectively. In both cases, blood lactate rate was significantly increased to higher level after electrical stimulation than before. Moreover, the rate of change in the average of blood lactate rate at both duty cycles also showed significant differences. CPK rate was boosted to 301.82% at 50% duty cycle after experiment and 321.35% at 20% duty cycle after experiment respectively. In both cases, CPK rate was remarkably boosted to higher level after stimulation than before (p<.05). However, there was not any significant difference in the rate of change in average CPK at both duty cycles (p<.05). GOT rate was significantly boosted up to 38.97% at 50% duty cycle after experiment (p<.05), while it was slightly increased to 1.68% at 20% duty cycle after experiment without any significant difference. Rather, GPT rate dropped slightly at both duty cycles after experiment, but there was not any significant difference. Although blood lactate and GOT were relatively less generated at 20% duty cycle after electrical stimulation than at 50% duty cycle, the change of duty cycle didn't have any significant influence on CPK rate. In this regard, this study failed to come any consistent conclusion about the association between change of duty cycle and muscle fatigue. Therefore, it is advisable that follow-up studies seek various ways to a little more effectively apply electrical stimulation to laboratory animals by avoiding their muscle fatigue. GOT rate was significantly boosted up to 38.97% at 50% duty cycle after experiment (p<.05), while it was slightly increased to 1.68% at 20% duty cycle after experiment without any significant difference. Rather, GPT rate dropped slightly at both duty cycles after experiment, but there was not any significant difference. Although blood lactate and GOT were relatively less generated at 20% duty cycle after electrical stimulation than at 50% duty cycle, the change of duty cycle didn't have any significant influence on CPK rate. In this regard, this study failed to come any consistent conclusion about the association between change of duty cycle and muscle fatigue. Therefore, it is advisable that follow-up studies seek various ways to a little more effectively apply electrical stimulation to laboratory animals by avoiding their muscle fatigue.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.854-857
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• 2008

무선 센서 네트워크의 센서 노드는 내부 전원을 사용함으로 인해 수명이 제한적이다. 기존의 여러 MAC 프로토콜은 무선 센서 네트워크에서 에너지 절약을 위해 sleep/listen cycle을 스케쥴링한다. 또한, MAC프로토콜의 duty-cycle은 사용자의 조정에 의해 낮은 duty cycle로 변화할 수 있으며, 이는 프레임에서 sleep 시간을 결정하게 된다. 이러한 duty cycle의 크기는 MAC 프로토콜의 성능에 직접적인 영향을 미친다. 본 논문에서는 NS-2 환경에서 서로 다른 duty cycle을 갖는 TEEM과 SMAC을 시뮬레이션하고 두 개의 프로토콜의 에너지 소비와 성능 측면에서 duty cycle을 분석한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• 대한전기학회논문지:전력기술부문A
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• 제55권10호
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• pp.399-409
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• 2006

This paper presents a novel method for satisfying the thermal comfort of indoor environment and reducing the summer peak demand power by minimizing the power consumption for an Air-conditioner within a space. Korea Electric Power Corporation (KEPCO) use the fixed duty cycle control method regardless of the indoor thermal environment. However, this method has disadvantages that energy saving depends on the set-point value of the Air-Conditioner and direct load control (DLC) has no net effects on Air-conditioners if the appliance has a lower operating cycle than the fixed duty cycle. In this paper, the variable duty cycle control method is proposed in order to compensate the weakness of conventional fixed duty cycle control method and improve the satisfaction of residents and the reduction of peak demand. The proposed method estimates the predict mean vote (PMV) at the next step with predicted temperature and humidity using the back propagation neural network model. It is possible to reduce the energy consumption by maintaining the Air-conditioner's OFF state when the PMV lies in the thermal comfort range. To verify the effectiveness of the proposed variable duty cycle control method, the case study is performed using the historical data on Sep. 7th, 2001 acquired at a classroom in Seoul and the obtained results are compared with the fixed duty cycle control method.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.51-58
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• 2013

본 논문에서는 고속 SoC 설계시 필요한 클록킹 회로의 핵심 소자인 클록 듀티 보정회로 (Duty-Cycle Corrector: DCC)를 소개한다. 종래의 아날로그 피드백 DCC와 디지털 피드백 DCC의 구조와 동작에 대해 비교 분석한다. 듀티-보정 레인지의 확장과 동작 주파수 및 듀티-보정 정확도의 향상을 위해 아날로그와 디지털 DCC의 장점을 결합한 새로운 혼성-모드 피드백 DCC를 소개한다. 특히, 혼성-모드 DCC의 핵심 구성 회로인 듀티-앰프 (Duty-Cycle Amplifier: DCA)의 구조와 설계에 대해 자세히 소개한다. 싱글-스테이지 DCA와 투-스테이지 DCA 기반의 두 개의 혼성-모드 DCC가 각각 0.18-${\mu}m$ CMOS 공정으로 설계되었고, 투-스테이지 DCA기반 DCC가 더 넓은 듀티-보정 레인지와 더 적은 듀티-보정 에러를 갖고 있음을 증명하였다.

• 한국통신학회논문지
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• 제39B권10호
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• pp.691-699
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• 2014

네트워크 수명을 연장시키기 위해 무선 센서 네트워크에서는 idle listening에 소비되는 에너지를 줄일 수 있는 듀티-사이클 MAC 프로토콜들이 제안되었다. 일반적인 듀티-사이클 MAC 프로토콜에서 각 센서 노드는 잔여 에너지양을 기반으로 듀티-사이클 주기를 계산한다. 그러나 에너지 수집이 가능한 센서 네트워크에서 기존 듀티-사이클 주기는 에너지 수집률이 높은 센서 노드에 불필요한 sleep 지연을 발생시킨다. 따라서 우리는 이전 연구에서 잔여 에너지양과 에너지 수집률을 함께 고려하여 듀티 사이클-주기를 조절하는 듀티-사이클 스케줄링 기법을 제안하였다. 그러나 이러한 듀티-사이클 MAC 프로토콜들은 듀티 사이클-주기 변화에 따른 성능 차이를 고려하지 않고 듀티-사이클 주기를 항상 선형적으로 조절하므로, 응용의 요구사항에 맞는 최적의 듀티 사이클 주기를 얻지 못한다. 본 논문에서는 듀티-사이클 주기를 계산하는 세 가지 기법들을 제안하고 그 결과에 대해 분석한다. 실험을 통해 제안된 기법들이 기존 듀티-사이클 스케줄링 기법에 비해 네트워크 수명, 단대단 패킷 전송 시간과 패킷 전송률을 각각 최대 23%, 44%, 31% 증가시킴을 확인하였다.

• Journal of Power Electronics
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• 제13권5호
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• pp.757-765
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• 2013

For conventional interleaved two-phase forward converters with a common output inductor, the maximum duty cycle is 0.5, which limits the voltage range and increases the difficulty of the transformer's optimization. A new two-phase hybrid forward converter with series-parallel auto-regulated transformer windings is presented in this paper. With interleaved control signals for the two phases, the secondary windings of the transformers can work in series when the duty cycle is larger than 0.5, and they can work in parallel when duty cycle is lower than 0.5. Therefore, the maximum duty cycle is extended and the turns ratio of the transformer can be optimized. Duty cycle dependent auto-regulated windings result in the steady states of the converter being different in different duty cycle ranges (D>0.5 and D<0.5). Fortunately, the steady state gains of the proposed hybrid converter are identical at different duty cycle ranges, which means a stepless shift between two states. A prototype is built to verify the theoretical analysis. A conventional control loop is compatible for the whole input voltage range and load range thanks to the stepless shifting between the different duty cycle ranges.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제6권4호
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• pp.1076-1089
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• 2012

Home automation networks are good environments for merging sensor networks and consumer electronics technologies. It is very important to reduce the energy consumption of each sensor node because sensor nodes operate with limited power based on a battery that cannot be easily replaced. One of the primary mechanisms for achieving low energy operation in energy-constrained wireless sensor networks is the duty-cycle operation, but this operation has several problems. For example, unnecessary energy consumption occurs during synchronization between transmission schedules and sleep schedules. In addition, a low duty-cycle usually causes more performance degradation, if the network becomes congested. Therefore, an appropriate control scheme is required to solve these problems. In this paper, we propose UDC (Unsynchronized Duty-cycle Control), which prevents energy waste caused by unnecessary preamble transmission and avoids congestion using duty-cycle adjustment. In addition, the scheme adjusts the starting point of the duty-cycle in order to reduce sleep delay. Our simulation results show that UDC improves the reliability and energy efficiency while reducing the end-to-end delay of the unsynchronized duty-cycled MAC (Media Access Control) protocol in sensor-based home automation networks.

• International journal of advanced smart convergence
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• 제7권4호
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• pp.19-26
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• 2018

One of the distinct features of Wireless Sensor Networks (WSNs) is duty cycling mechanism, which is used to conserve energy and extend the network lifetime. Large duty cycle interval introduces lower energy consumption, meanwhile longer end-to-end (E2E) delay. In this paper, we introduce an energy consumption minimization problem for duty-cycled WSNs. We have applied Q-learning algorithm to obtain the maximum duty cycle interval which supports various delay requirements and given Delay Success ratio (DSR) i.e. the required probability of packets arriving at the sink before given delay bound. Our approach only requires sink to compute Q-leaning which makes it practical to implement. Nodes in the different group have the different duty cycle interval in our proposed method and nodes don't need to know the information of the neighboring node. Performance metrics show that our proposed scheme outperforms existing algorithms in terms of energy efficiency while assuring the required delay bound and DSR.