• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.215.2-215.2
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• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.583-586
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• 2009

A 14.1" XGA (1024${\times}$768) LCD panel with Integrated Black Data Insertion (IBDI) has been world first developed successfully based on the integrated amorphous Silicon TFT gate driver which we previously introduced. The notable features compared with the conventional integrated a-Si TFT gate driver circuit are that the circuit consists of Dual buffer, Carry buffer structure, and Q-node cross charging for stable signal scanning characteristic and prevention of coupling between signal lines.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.311-311
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• 2016

최근 고성능 디스플레이 개발이 요구되면서 기존 비정질 실리콘(a-Si)을 대체할 산화물 반도체에 대한 연구 관심이 급증하고 있다. 여러 종류의 산화물 반도체 중 a-IGZO (amorphous indium-gallium-zinc oxide)가 높은 전계효과 이동도, 저온 공정, 넓은 밴드갭으로 인한 투명성 등의 장점을 가지며 가장 연구가 활발하게 보고되고 있다. 기존에는 SG(단일 게이트) TFT가 주로 제작 되었지만 본 연구에서는 DG(이중 게이트) 구조를 적용하여 고성능의 a-IGZO 기반 박막 트랜지스터(TFT)를 구현하였다. SG mode에서는 하나의 게이트가 채널 전체 영역을 제어하지만, double gate mode에서는 상, 하부 두 개의 게이트가 동시에 채널 영역을 제어하기 때문에 채널층의 형성이 빠르게 이루어지고, 이는 TFT 스위칭 속도를 향상시킨다. 또한, 상호 모듈레이션 효과로 인해 S.S(subthreshold swing)값이 낮아질 뿐만 아니라, 상(TG), 하부 게이트(BG) 절연막의 계면 산란 현상이 줄어들기 때문에 이동도가 향상되고 누설전류 감소 및 안정성이 향상되는 효과를 얻을 수 있다. Dual gate mode로 동작을 시키면, TG(BG)에는 일정한 positive(or negative)전압을 인가하면서 BG(TG)에 전압을 가해주게 된다. 이 때, 소자의 채널층은 depletion(or enhancement) mode로 동작하여 다른 전기적인 특성에는 영향을 미치지 않으면서 문턱 전압을 쉽게 조절 할 수 있는 장점도 있다. 제작된 소자는 p-type bulk silicon 위에 thermal SiO2 산화막이 100 nm 형성된 기판을 사용하였다. 표준 RCA 클리닝을 진행한 후 BG 형성을 위해 150 nm 두께의 ITO를 증착하고, BG 절연막으로 두께의 SiO2를 300 nm 증착하였다. 이 후, 채널층 형성을 위하여 50 nm 두께의 a-IGZO를 증착하였고, 소스/드레인(S/D) 전극은 BG와 동일한 조건으로 ITO 100 nm를 증착하였다. TG 절연막은 BG 절연막과 동일한 조건에서 SiO2를 50 nm 증착하였다. TG는 S/D 증착 조건과 동일한 조건에서, 150 nm 두께로 증착 하였다. 전극 물질과, 절연막 물질은 모두 RF magnetron sputter를 이용하여 증착되었고, 또한 모든 patterning 과정은 표준 photolithography, wet etching, lift-off 공정을 통하여 이루어졌다. 후속 열처리 공정으로 퍼니스에서 질소 가스 분위기, $300^{\circ}C$ 온도에서 30 분 동안 진행하였다. 결과적으로 $9.06cm2/V{\cdot}s$, 255.7 mV/dec, $1.8{\times}106$의 전계효과 이동도, S.S, on-off ratio값을 갖는 SG와 비교하여 double gate mode에서는 $51.3cm2/V{\cdot}s$, 110.7 mV/dec, $3.2{\times}108$의 값을 나타내며 훌륭한 전기적 특성을 보였고, dual gate mode에서는 약 5.22의 coupling ratio를 나타내었다. 따라서 산화물 반도체 a-IGZO TFT의 이중게이트 구조는 우수한 전기적 특성을 나타내며 차세대 디스플레이 시장에서 훌륭한 역할을 할 것으로 기대된다.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1301-1304
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• 2008

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pull-down structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.17-22
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• 2004

We developed a new ANGLED display driving method which used both amplitude and pulse width modulation. For pulse width modulation, we divided a picture frame time into S sub-frames. For amplitude modulation, we used three OLED luminance(or current) levels which were controlled by TFT's gate voltages. By combining these two modulation methods, we obtained 35(=243) grey levels. And we designed a new data electrode driving circuit block with two shift registers without using DAC's. To verify the feasibility, we simulated the key circuit components by HSpice with TFT parameters extracted from current-voltage characteristics of 6${\mu}{\textrm}{m}$ channel length polysilicon TFT's. From the simulation results, we found that 320${\times}$240, dual scan, 243 grey level AMOLED display can be designed with this method.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.944-947
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• 2005

Highly stable gate driver circuit using a-Si TFT has been developed. The circuit has dual-pull down structure, in which bias stress to the TFTs is relieved by alternating applied voltage. The circuit has been successfully integrated in 4-in. QVGA and 14-in. XGA TFT-LCD with a normal a-Si process, which are stable for over 2,000 hours at $60^{\circ}C$. The enhancement of stability of the circuit is attributed to retarded degradation of pull-down TFTs by AC driving.