• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.473-476
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• 1998

ULSI 소자에서 폴리사이드 구조를 사용하고 dual 게이트 산화막에 대한 공정 특성을 최적화 하는 2스텝 게이트 산화막의 형성 공정에 관한 연구를 하였다. 이러한 특성의 측정은 HP4145B 파라메터 분석기와 C-V meter 그리고 multi-frequency LcR meter를 사용하여 2스텝 산화막의 공정 방법과 cleaning에 따른 게이트 사화막의 공정 특성에 대한 연관 관계로 연구하였다. I-V 특성 면에서는 G$_{ox}$ 80.angs.의 경우 base 210.angs.의 경우에서는 dual 210.angs.의 특성이 base 210.angs.에 비하여 상대적으로 열화된 특성을 나타내었다. CCST 결과에서는 G$_{OX}$ 80.angs.과 210.angs.에서 dual 게이트 산화막의 cleaning 방법으로 piranha cl'n 과 SCl cl'n 방법에서 우수한 결과를 얻을 수 있었다. 또한 게이트 전압의 벼화량에 대한 결과에서는 dual 산화막의 경우 초기상태에서는 호울포획 현상이 나타나다가 이후에는 전자포획 현상이 나타나는 결과를 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1481-1486
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• 2013

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1301-1304
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• 2008

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pull-down structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.193-196
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• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.239-239
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• 2013

For more than four decades, ion-sensitive field-effect transistor (ISFET) sensors that respond to the change of surface potential on a membrane have been intensively investigated in the chemical, environmental, and biological spheres, because of their potential, in particular their compatibility with CMOS manufacturing technology. Here, we demonstrate a new type of ISFET with dual-gate (DG) structure fabricated on ultra-thin body (UTB), which highly boosts sensitivity, as well as enhancing chemical stability. The classic ion-sensitive field-effect transistor (ISFET) has been confronted with chronic problems; the Nernstian response, and detection limit with in the Debye length. The super-coupling effects imposed on the ultra thin film serve to not only maximize sensitivity of the DG ISFET, but also to strongly suppress its leakage currents, leading to a better chemical stability. This geometry will allow the ISFET based biosensor platform to continue enhancement into the next decade.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.215.2-215.2
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• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.