• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.8
• /
• pp.582-586
• /
• 2013

In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.1
• /
• pp.27-32
• /
• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.8 s.111
• /
• pp.707-712
• /
• 2006

In this paper, dual bias control circuit and PBG(Photonic BandGap) structure have been employed to improve PAE(Power Added Effciency) of the Doherty amplifier on Input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal and PBG structure has been employed on the output port of Doherty amplifier. The proposed Doherty amplifier using dual bias controlled circuit and PBG has been improved the average PAE by 8%, $IMD_3$ by -5 dBc. And proposed Doherty amplifier has a high efficiency more than 30% on overall input power level, respectively.

• Journal of Biomedical Engineering Research
• /
• v.26 no.1
• /
• pp.17-22
• /
• 2005

Small animal PET using a dual layer phoswich detector has been developed to obtain high and uniform spatial resolution. In this study, a simple analytic model to optimize the lengths of a dual layer phoswich detector was derived and validated by Monte Carlo simulation. For a small animal PET scanner with a 10㎝ ring diameter, the optimal length of the phoswich detector consisting of various crystal materials, such as LSO and LuYAP, were calculated analytically and validated using GATE. The detector module consisted of 8×8 arrays of crystals, with each phoswich detector element having a 2㎜×2㎜ sensitive area. The total crystal length was fixed to 20㎜. The optimal lengths of the phoswich detector layers, as functions of the crystal materials and order, conveniently derived by the analytic equation, showed good agreement with those estimated by the time consuming simulation. The simple analytical model can be used for the fast and accurate design of an optimal phoswich detector for small animal PET to achieve high spatial resolution and uniformity.

• ETRI Journal
• /
• v.27 no.1
• /
• pp.81-88
• /
• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.9
• /
• pp.1614-1618
• /
• 2007

We have demonstrated the experimental results to obtain the immunity of FN (Fowler Nordheim) stress for S-RCAT (Spherical-Recess Cell Array Transistor) which has been employed to meet the requirements of data retention time and propagation delay time for sub-100-nm mobile DRAM (Dynamic Random Access Memory). Despite of the same S-RCAT structure, the immunity of FN stress of S-RCAT depends on the process condition of gate oxidation. The S-RCAT using DPN (decoupled plasma nitridation) process showed the different degradation of device properties after FN stress. This paper gives the mechanism of FN-stress degradation of S-RCAT and introduces the improved process to suppress the FN-stress degradation of mobile DRAM.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.4
• /
• pp.575-581
• /
• 2000

In this paper, a new active phase shifter is proposed using a vector sum method, and a unique digital phase control method of the circuit is suggested. The proposed scheme was designed and implemented using a Wilkinson power combiner/divider, a branch line 3 dB quadrature hybrid coupler and variable gain amplifiers (VGAs) using gate FETs(DGFETs). Furthermore, it was also shown that the proposed scheme is more efficient and works properly with the digital phase control method.

• Journal of Sensor Science and Technology
• /
• v.29 no.1
• /
• pp.68-73
• /
• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Journal of Biosystems Engineering
• /
• v.34 no.2
• /
• pp.95-105
• /
• 2009

A method was proposed which employed control of the drop location of fertilizer particles on a spinner disc to optimize the spread pattern uniformity. The system contained an optical sensor as a feedback mechanism, which measured discharge velocity and location, as well as particle diameters to predict a spread pattern of a single disc. Simulations showed that the feed gate adaptation algorithm produced high quality patterns for any given application rate in the dual disc spreader. The performance of the feed gate control method was assessed using data collected from a Sulky spinner disc spreader. The results showed that it was always possible to find a spread pattern with an acceptable CV lower than 15%, even though the spread pattern was obtained from a rudimentary flat disc with straight radial vanes. A mathematical optimization method was used to find the initial parameter settings for a specially designed experimental spreading arrangement, which included the feed gate control system, for a given flow rate and swath width. Several experiments were carried out to investigate the relationship between the gate opening and flow rate, disc speed and particle velocity, as well as disc speed and predicted landing location of fertilizer particles. All relationships found were highly linear ($r^2$ > 0.96), which showed that the time-of-flight sensor was well suited as a feedback sensor in the rate and uniformity controlled spreading system.