• JSTS:Journal of Semiconductor Technology and Science
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• 제3권1호
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

• 한국전자파학회논문지
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• 제17권8호
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• pp.707-712
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• 2006

본 논문에서는 이중 바이어스 조절과 PBG 구조를 이용하여 Doherty 증폭기의 효율을 개 선하였다. PBG 구조를 출력 정합 회로에 구현하였으며, 이중 바이어스 조절을 carrier amplifier에 적용하여 낮은 입력 레벨에서도 Doherty 증폭기의 효율을 개선할 수 있었다. 제안된 구조를 이용한 Doherty 증폭기는 기존의 전력 증폭기에 비해 PAE는 8%, $IMD_3$는 -5 dBc 개선하고, 모든 입력 전력 레벨에서 30% 이상의 고효율을 가질 수 있었다.

• 대한의용생체공학회:의공학회지
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• 제26권1호
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• pp.17-22
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• 2005

Small animal PET using a dual layer phoswich detector has been developed to obtain high and uniform spatial resolution. In this study, a simple analytic model to optimize the lengths of a dual layer phoswich detector was derived and validated by Monte Carlo simulation. For a small animal PET scanner with a 10㎝ ring diameter, the optimal length of the phoswich detector consisting of various crystal materials, such as LSO and LuYAP, were calculated analytically and validated using GATE. The detector module consisted of 8×8 arrays of crystals, with each phoswich detector element having a 2㎜×2㎜ sensitive area. The total crystal length was fixed to 20㎜. The optimal lengths of the phoswich detector layers, as functions of the crystal materials and order, conveniently derived by the analytic equation, showed good agreement with those estimated by the time consuming simulation. The simple analytical model can be used for the fast and accurate design of an optimal phoswich detector for small animal PET to achieve high spatial resolution and uniformity.

• ETRI Journal
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• 제27권1호
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• 전기학회논문지
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• 제56권9호
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• pp.1614-1618
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• 2007

We have demonstrated the experimental results to obtain the immunity of FN (Fowler Nordheim) stress for S-RCAT (Spherical-Recess Cell Array Transistor) which has been employed to meet the requirements of data retention time and propagation delay time for sub-100-nm mobile DRAM (Dynamic Random Access Memory). Despite of the same S-RCAT structure, the immunity of FN stress of S-RCAT depends on the process condition of gate oxidation. The S-RCAT using DPN (decoupled plasma nitridation) process showed the different degradation of device properties after FN stress. This paper gives the mechanism of FN-stress degradation of S-RCAT and introduces the improved process to suppress the FN-stress degradation of mobile DRAM.

• 정보와 통신
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• 제25권12호
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 한국전자파학회논문지
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• 제11권4호
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• pp.575-581
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• 2000

본 논문에서는 Vector Sum 방법을 이용한 새로운 구조의 능동 위상천이기를 제안하였고 그 위상천이기를 제 어할 독특한 디지털 방식의 위상 제어 방법을 제시하였다. 제안한 새로운 구조의 능동 위상천이기는 Wilkinson power combiner/divider, branch line 3 dB quadrature hybrid coupler, 그리고 dual gate FET(DGFET)를 사용 한 가변 이득 증폭기(VGA)를 이용하여 설계.제작하였다. 그리고 제작된 능동 위상천이기를 디지털 방식으로 동작시킴으로써 제안된 구조가 효율적으로 잘 동작하고 또한 제시된 디지혈 방식으로 제어하는 방법이 타당함을 보였다.

• 센서학회지
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• 제29권1호
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Journal of Biosystems Engineering
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• 제34권2호
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• pp.95-105
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• 2009

A method was proposed which employed control of the drop location of fertilizer particles on a spinner disc to optimize the spread pattern uniformity. The system contained an optical sensor as a feedback mechanism, which measured discharge velocity and location, as well as particle diameters to predict a spread pattern of a single disc. Simulations showed that the feed gate adaptation algorithm produced high quality patterns for any given application rate in the dual disc spreader. The performance of the feed gate control method was assessed using data collected from a Sulky spinner disc spreader. The results showed that it was always possible to find a spread pattern with an acceptable CV lower than 15%, even though the spread pattern was obtained from a rudimentary flat disc with straight radial vanes. A mathematical optimization method was used to find the initial parameter settings for a specially designed experimental spreading arrangement, which included the feed gate control system, for a given flow rate and swath width. Several experiments were carried out to investigate the relationship between the gate opening and flow rate, disc speed and particle velocity, as well as disc speed and predicted landing location of fertilizer particles. All relationships found were highly linear ($r^2$ > 0.96), which showed that the time-of-flight sensor was well suited as a feedback sensor in the rate and uniformity controlled spreading system.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 1998년도 추계학술대회논문집:21세기에 대비한 지능형 통합항만관리
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• pp.19-49
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• 1998

I try to introduce three types of designs for automatic container operating system which are designed by Institute of Japan Port Research in 1996. Each types are designedto fit with the situations of Japan Port. 'A'type of these designs adapts Dual Container Crane, AGV, RMG, etc. 'B'type of these designs adapts Dual Container Crane, AGV, OHBC, RTG. And 'C'type of these designs adapts Single Container Crane, AGV, OHBC, etc. Even if three designs are introduced, they have some problems to solve for the future. They are Lashing work, Refeer container problem, check for container and seal in main gate, Establishing EDI NETWORK, etc. I expect that this paper will be a helps to development of our port industry.