• Journal of Korean Institute of Industrial Engineers
• /
• v.23 no.4
• /
• pp.699-708
• /
• 1997

Production control is usually composed of due-dote assignment, production input control, and priority dispatching rule. A production input control(PIC) is mainly to control the WIP level on the shop floor. On the other hand, a priority dispatching rule(PDR) is mainly to control the tardiness/earliness of on order and number of tardy jobs. Therefore, if we select a particular PIC which can control only a particular performance measure(i.e., tardiness), it may cause worsening other performance measure(i.e., WIP level, shopfloor time, etc.) This newly developed production input control, DRD(Dual Release-Dates), is mainly designed to control the WIP level on the shop floor by employing two different release-dates of an order(earliest release. date and latest release-date and the release condition (relationship between the current WIP level and the pre-defined maximum WIP level) while trying to meet the due-date of the order.

• Journal of Power Electronics
• /
• v.1 no.2
• /
• pp.78-87
• /
• 2001

A new high-power step-up based on the two-module parallel-input (PISO) modular dual inductor-fed push-pull converter is proposed. The proposed converter is operated at a constant duty cycle and employs and auxiliary circuit to control the output voltage with a phase-shift between two modules. It shows a high efficiency due to the greatly reduced switch turn-off stress. It also shows a high and linear voltage conversion ratio, low current stress in the output capacitor, and fast control-to-output dynamics. The operation principles and the mathematical models of the proposed converter are presented. Features of the proposed converter are discussed in comparison with the two-module PISO modular dual inductor-fed push-pull converter. Also, experimental results from a 50kHz, 800W, 350 Vdc prototype with an input voltage range of 20-32 Vdc are provided to confirm the validity of the proposed converter. The new converter compares favorably with the conventional counterpart, and is considered well siuted to high-power step-up applications.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.267-274
• /
• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• Journal of Power Electronics
• /
• v.18 no.2
• /
• pp.482-491
• /
• 2018

The practical design methodology of a three-phase dual active bridge (3ph-DAB) converter applied to low voltage direct current (LVDC) applications is proposed by using a mathematical model based on the steady-state operation. An analysis of the small-signal model (SSM) is important for the design of a proper controller to improve the stability and dynamics of the converter. The proposed lead-lag controller for the 3ph-DAB converter is designed with a simplified SSM analysis including an equivalent series resistor (ESR) for the output capacitor. The proposed controller can compensate the effects of the ESR zero of the output capacitor in the control-to-output voltage transfer function that can cause high-frequency noises. In addition, the performance of the power converter can be improved by using a controller designed by a SSM analysis without additional cost. The accuracy of the simplified SSM including the ESR zero of the output capacitor is verified by simulation software (PSIM). The design methodology of the 3ph-DAB converter and the performance of the proposed controller are verified by experimental results obtained with a 5-kW prototype 3ph-DAB converter.

• Proceedings of the IEEK Conference
• /
• 2007.07a
• /
• pp.433-434
• /
• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.8-10
• /
• 2019

In this paper, a bidirectional three-phase push pull converter is analyzed for the high power, wide voltage range applications. From comparison analysis of two switching methods: PWM plus phase-shift (PPS) and dual-asymmetric PWM (DAPWM) with the effect of dead-time, the proposed hybrid control is aimed to reduce the circulating current under wide voltage range operation. Value of leakage inductance effect to the peak current value, current stress and conduction loss in facing the load variation. Trade-off between power range and slew rate of transformer current was analyzed for properly selecting value of the transformer leakage inductance. Experimental results from a 22-kW prototype are provided to validate the proposed concept.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.269-272
• /
• 2002

This work describes the use of neural networks (NNs) for interpreting voltammetric data, i.e., current-voltage spectra that obtained from the electrochemical reaction of analyte species at a gold electrode. Current-voltage spectra of glucose, fructose and ascorbic acid in mixtures obtained from dual-pulse staircase voltammetry (DPSV) was in the form of the mixed responses contain characteristics of the individual analytes approximately in proportion to their concentration. Extraction of individual analyte concentration from combined data was subsequently achieved using NNs. The combination of DPSV and NNs opens a possibility for simultaneous determination of mixtures of the species for fruit juices quality monitoring.

• Journal of Institute of Convergence Technology
• /
• v.3 no.1
• /
• pp.19-23
• /
• 2013

This study is concerned with air-conditioning system in use of thermoelectric device. It is introduced that the well designed structures for better cooling & heating performance with high efficiency. And also it is performed that the system performance test of four types trial products for the use of hybrid commercial vehicle. System performance is affected by many component parts, especially heat sink design & power control method. It is applied that dual extrusive fin tube with buffer zone for the effective radiating of circulating liquid in tube. And also it is applied that power supply method with constant-current system. It is attained that system cooling capacity is 1.2kW, COP is 0.95.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.4
• /
• pp.336-344
• /
• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.5
• /
• pp.379-386
• /
• 2009

This paper investigates the operation of ITER(International Thermonuclear Experimental Reactor) Vertical Stabilization(VS) converter with circulating current. The VS converter has two subunits in parallel. The subunit is composed two back-to-back 12 pulse thyristor converter in series. The circulating current free technique can not always maintain the closed path for the load current because of a dead time zone of the converter operation at the region of the load current inversion. The complex circulation current technique for the load current inversion with VS converter can achieve the fast response and always maintain the closed path for the load curret. The paper proposes the new circulating current algorithm for the load current inversion of ITER VS converter and proves the performance of the circulating current technique with PSIM simulation study.