• Journal of Power Electronics
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• v.18 no.1
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• pp.1-10
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• 2018

Recently, the nine-switch inverter has been proposed as a dual output inverter. To date, studies on the control strategies for NSIs have been mostly combined with their application. However, in this paper, a mathematical model and control strategy for nine-switch inverters has been proposed in view of the topology. A switching function model and equivalent circuit model of a nine-switch inverter have been built in ${\alpha}{\beta}$ coordinates. Then, a novel current observer with an improved integrator is proposed based on the switching function model, and a direct power control strategy is proposed. No current sensors are used in the proposed strategy, and only two voltage sensors are employed. The performance of the proposed control method is verified by simulation and experimental results.

• Journal of Ocean Engineering and Technology
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• v.36 no.1
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• pp.21-31
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• 2022

In recent years, various studies have been conducted on oscillating-water-column-type wave energy converters (OWC-WECs) with multiple chambers with the objective of efficiently utilizing the limited space of offshore/onshore structures. In this study, a numerical investigation based on a numerical wave tank was conducted on single, dual, and triple OWC chambers to examine the hydrodynamic performances and the energy conversion characteristics of the multiple water columns. The boundary value problem with the Laplace equation was solved by using a numerical wave tank based on a finite element method. The validity of the current numerical method was confirmed by comparing it with the measured data in the previous experimental research. We undertook a series of numerical simulations and observed that the water column motion of sloshing mode in a single chamber can be changed into the piston motion of different phases in multiple OWC chambers. Therefore, the piston motion in the multiple chambers can generate considerable airflow at a specific resonant frequency. In addition, the division of the OWC chamber results in a reduction of the time-dependent variability of the final output power from the device. As a result, the application of the multiple chambers leads to an increase of the energy conversion performance as well as a decrease of the variability of the wave energy converter.

• Journal of Korean Port Research
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• v.11 no.2
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• pp.273-280
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• 1997

Recently the importance of the cargo handling equipments in a port has been increasing to get strong competition from other ports. Many ports are making efforts to modernize their cargo handling equipments. The kernel technology of such equipments is the speed control of DC motor which is used as an essential part of them. In this paper, we discuss the speed control of a DC motor as a basic work for building cargo handling equipments in a port. DC Motors are still widely used in industrial fields, as driving power motor for electrical fields. DC drives, being easy to control, are widely used in many variable-speed and position control drive system. Traditional analog control circuits used in such applications have many disadvantages. Complex control schemes are difficult to implement with analog components. All these factor and invention of the microprocessor has made it possible to use digital control circuits, using microprocessing system. These digital circuits have been found to be reliable, flexible, and also immune to noise. In this paper it presents the speed control of a SCR DC motor driver which using dual converter by 80c196kc microprocessor. We developed a thyristor power amplifier which does not cause damage thyristor because it is designed to prevent triggering the two SCRs in the same arm simultaneously. And it was analyzed voltage and currents wave at reactive load.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.5
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• pp.587-592
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• 2018

Because the brightness of an AMOLED is determined by the flowing current, each pixel of AMOLED operates via A current driving method. Therefore, it is necessary to supply power to adjust the amount of current according to THE user's requirement for AMOLED driving. In this study, an IP driver block was designed and a simulation was conducted for an AMOLED display, which supplies power as selected by users. The IP driver design focused on regulating the output power due to the OLED characteristics for the diode electric current according to the voltage to be activated by pulse-skipping mode (PSM) under low loads, and 1.5 MHz pulse-width modulation (PWM) for medium/high loads. The IP driver was designed to eliminate the ringing effects appearing from the dis-continue mode (DCM) of the step-up converter. The ringing effects destroy the power switch within the IC, or increase the EMI to the surrounding elements. The IP driver design minimized this through a ringing killer circuit. Mobile applications were considered to enable true shut-down capability by designing the standby current to fall below $1{\mu}A$ to disable it. The driver proposed in this paper can be applied effectively to the same system as the AMOLED display dual power management circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Resources Recycling
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• v.11 no.6
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• pp.3-11
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• 2002

Recently, waste printed circuit board (PCB) has significantly increased in its amount due to the rapid development of electronic industries. Since several kinds of noxious materials and also valuable metals are contained in it, the waste PCB is in an urgent need of recycling for the dual purposes for the prevention of environmental pollution and recovery of valuable resources. Also, the catalyst which equipped in the exhaust pipes of automobiles to reduce emission of air pollutants contains precious met-als so that their recovery from the waste auto-catalysts is required. In this study, the recovery of valuable metals from waste PCB and auto-catalyst by arc furnace melting process has been investigated, which is known to be very stable and suitable f3r less production of pollutants due to its high operating temperature. The effect of the kind of flux on the recovery of precious metals was examined by using quicklime, converter slag, and copper slag as the flux. In addition, the influence of direct and alternating current and the applying direction of direct current has been investigated. It was observed that using converter or copper slag as a flux was more desirable for a higher efficiency in the precious metal recovery compared with quicklime. For the effect of current, application of direct current taking the bottom as a negative pole generally showed a better efficiency for the extraction of valuable metals from waste PCB, which was also observed for the case of waste auto-catalyst. The average recovery of precious metals from both wastes by arc furnace melting process was very high, which was up to in the range of 95～97%.

• Journal of electromagnetic engineering and science
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• v.18 no.3
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.393-400
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• 2014

In this paper, we have designed the transmitter for earth station terminal operating with military geostationary satellite on Ka-band that is complied with MIL-STD-188-164A. The designed antenna of this terminal is dual-offset gregorian reflector which is consist of corrugated horn and iris polarizer, othermode transducer. This antenna meets radiation pattern and transmit EIRP spectral density requirements in this standard. The designed RF systems of this terminal are consist of Block Up Converter(BUC) converting frequency band from IF to Ka band and SSPA having low-power consumption and compact light-weight using the pHEMT MMIC compound devices. This RF systems applied with VSWR, spurious/harmonic suppression, output flatness and phase noise requirement in this standard.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.