• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권4호
• /
• pp.458-466
• /
• 2012

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

• Journal of electromagnetic engineering and science
• /
• 제3권2호
• /
• pp.140-146
• /
• 2003

In this paper, the design of a channel filter and its group-delay-and-amplitude equalizer is carried out for the Ka-band satellite transponder subsystem. The 8th order dual-mode filter is employed for high selectivity around the band-edges with an elliptic-integral function response and has an in-line configuration. The 2-pole, reflection-type, group-delay equalizer is designed and manufactured to reduce the group-delay and amplitude variation, which can be large for such a high order filter. It is noted that in both the filter and equalizer, adopting the dual-mode coupling mechanism leads to less mass and volume. Through measurement, the performance of the realized group-delay-equalized filter is shown to meet the equipment requirements and to be appropriate for the satellite input multiplexer.

• 전자공학회논문지D
• /
• 제34D권10호
• /
• pp.53-59
• /
• 1997

In this paper, we present a 20 GHz low-loss dual-mode channel filter designed by using mode matching method. The performance of dual-mode channel filter mainly depends on iris characteristics. Therefore the exact design of iris is the key point to get good frequncy response of the filter. MOde matching technique is widely used ot design several kinds of waveguide filters because it is simple in theory and can easily calculate the scattering matrices at the discontinuities with simple structure like iris coupled filters. Additionally the effect for finite thickness of the iris in the dual-mode cavity iflter is analyzed by te full-wave method, providing the exact filter implementation without trial and error.

• 전기학회논문지P
• /
• 제57권3호
• /
• pp.260-264
• /
• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
• /
• pp.342-344
• /
• 2005

We have simulated a symmetric dual-gate TFT which has triple floating n+ channel to improve the on-current of the dual-gate TFT. We achieved a low hole concentration at the source and channel junction causes the improvement the potential barrier so that we observed the reduction of the kink-effect. In this paper, we observed the reduction of the kink-effect compared with the conventional single-gate TFT and the improvement of the on-current compared with the conventional dual-gate TFT.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제8권3호
• /
• pp.778-798
• /
• 2014

This paper proposes a novel exposed-terminal-eliminated medium access control (ETE-MAC) protocol by combining channel reservation, collision avoidance and concurrent transmissions to improve multi-access performance of the multihop wireless networks. Based on the proposed slot scheduling scheme, each node senses the control channel (CCH) or the data channel (DCH) to accurately determine whether it can send or receive the corresponding packets without collisions. Slot reservation on the CCH can be simultaneously executed with data packet transmissions on the DCH. Therefore, it resolves the hidden-terminal type and the exposed-terminal type problems efficiently, and obtains more spatial reuse of channel resources. Concurrent packet transmissions without extra network overheads are maximized. An analytical model combining Markov model and M/G/1 queuing theory is proposed to analyze its performance. The performance comparison between analysis and simulation shows that the analytical model is highly accurate. Finally, simulation results show that, the proposed protocol obviously outperforms the link-directionality-based dual-channel MAC protocol (DCP) and WiFlex in terms of the network throughput and the average packet delay.

• Transactions on Electrical and Electronic Materials
• /
• 제16권5호
• /
• pp.254-259
• /
• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• 한국인터넷방송통신학회논문지
• /
• 제22권4호
• /
• pp.59-65
• /
• 2022

본 논문에서는 디지털 능동위상배열 안테나를 간략히 소개하고 주 빔의 부엽을 차단하기 위해 적용된 이중 채널 부엽 차단 빔 형성 방법에 대해 기술하였다. 그리고 안테나 주 빔 및 부엽 차단 빔 설계 결과와 안테나 근접전계 측정 결과로부터 안테나 성능을 검증하였다. 다음으로 기존의 이중 채널 부엽 차단 빔 운용 방식 보다 채널수를 줄이기 위해 단일 채널 부엽 차단 빔 형성 방법을 제안하고, 제안한 방법으로 부엽 차단 안테나에 대한 소자별 가중치 분포를 설계하였다. 마지막으로 설계된 단일 채널 부엽 차단 빔 패턴과 차단 능력을 검증하고 이중 채널 부엽 차단 빔과 비교하였다. 또한, 디지털 능동위상배열 안테나의 수신 근접전계 시험을 통해 측정한 이중 채널 부엽 차단 빔과 제안된 단일 채널 부엽 차단 빔 패턴 및 부엽 차단 성능을 비교/검증함으로써 제안된 부엽 차단 빔 형성 방법에 대한 유효성을 확인하였다.

• 한국전자파학회논문지
• /
• 제13권3호
• /
• pp.225-236
• /
• 2002

본 논문에서는 동일채널 이중편파를 적용하는 디지털무선중계장치의 직교편파간섭을 제거할 목적으로 직교편파간섭제거기(XPIC)의 이론적 모델링, 디지털 설계를 분석하였다. 또한 유한임펄스응답 여파기를 이용한 복소 시간영역 적응등화기(ATDE)를 설계하고, 이를 이용한 XPIC의 구조 및 제어방법을 ATDE와의 연동하여 제시하였다. XPIC와 ATDE를 연동으로 약 25㏈ 이상의 시그너쳐(signature)와 약 23㏈ 이상의 XPIC 개선인자를 얻을 수 있음을 모의실험으로 보였다. 설계된 직편파간섭제거기의 동작검증을 위해 동일채널 이중편파용의 64-QAM모뎀과 연동하여 탭의 수, 알고리즘의 수렴, 장치의 성능, 직교편파간섭제거기의 개선인자에 대한 결과도 검토하였다.

• 설비공학논문집
• /
• 제22권11호
• /
• pp.760-766
• /
• 2010

Excessive heat occurs during semiconductor manufacturing process. Thus, precise control of temperature is required to maintain constant chamber-temperature and also wafer-temperature in the chamber. Compared to an industrial chiller, semiconductor chiller's power consumption is very high due to its continuous operation for a year. Considering the high power consumption, it is necessary to develop an energy efficient chiller by optimizing operation control. Therefore, in this study, a semiconductor chiller is experimentally investigated to suggest energy-saving direction by conducting load change, temperature rise and fall and control precision experiments. The experimental study shows the cooling capacity of dual-channel chiller rises over 30% comparing to the conventional chiller. The time and power consumption in the temperature rising experiment are 43 minutes and 8.4 kWh, respectively. The control precision is the same as ${\pm}1^{\circ}C$ at $0^{\circ}C$ in any cases. However, it appears that the dual channel's control precision improves to ${\pm}0.5^{\circ}C$ when the setting temperature is over $30^{\circ}C$.