• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2000년도 종합학술발표회 논문집 Vol.10 No.1
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• pp.71-74
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• 2000

본 논문에서는 무선LAN용으로 사용할 수 있는 마이크로 스트립을 이용한 대역동과 필터를 설계하였다. 기존의 링이나 square loop의 구조를 이용한 공진기와는 다르게 cross loop 와 meander loop의 구조를 이용한 공진기를 혼합한 형태로써 크기가 상당히 줄어든 새로운 구조와 BandPass Filter를 설계하였다.

• 대한전기학회논문지
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• 제43권5호
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• pp.827-837
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• 1994

This paper presents robustness propertis of the Kalman Fiter and the associated LQG/LTR method for linear time-invariant output-delayed systems. It is shown that, even for minimum phase plants, the LQG/LTR method can not recover the target loop transfer function. Instead, an upper bound on the recovery error is obtained using an upper bound of the solution of the Kalman filter Riccati equations. Finally, some dual properties between output-delayed systems and input-delayed systems are exploited.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.227-233
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• 2006

In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1614-1622
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• 2014

A novel equivalent flux sliding-mode observer (SMO) is proposed for dual three-phase interior permanent magnet synchronous motor (DT-IPMSM) drive system in this paper. The DT-IPMSM has two sets of Y-connected stator three-phase windings spatially shifted by 30 electrical degrees. In this method, the sensorless drive system employs a flux SMO with soft phase-locked loop method for rotor speed and position estimation, not only are low-pass filter and phase compensation module eliminated, but also estimation accuracy is improved. Meanwhile, to get the regulator parameters of current control, the inner current loop is realized using a decoupling and diagonal internal model control algorithm. Experiment results of 2MW-level DT-IPMSM drives system show that the proposed method has good dynamic and static performances.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.161-167
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• 1993

This paper presents robustness properties of the Kalman Filter ad the associated LQG/LTR method for linear time-invariant systems having delays in both the state and output. A circle condition relating to the return difference matrix associated with the Kalman filter is derived. Using this circle condition, it is shown that the Kalman filter guarantees(1/2, .inf.) gain margin and .+-.60.deg. phase margin, which are the same as those for nondelay systems. However, it is shown that, even for minimum phase plants, the LQG/LTR method can not recover the target loop transfer function. Instead, an upper bound on the recovery error is obtained using an upper bound of the solution of the Kalman filter Riccati equations. Finally, some dual properties between output-delated system and input-delayed systems are exploited.

• Journal of Power Electronics
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• 제12권3호
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• pp.458-467
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• 2012

Single phase converters suffer from ripple power pulsating at twice the line frequency. The ripple power is usually absorbed by a bulky capacitor bank and/or a dedicative LC resonant link, resulting in a low power density and a high cost. An alternative solution is using a dc link active power filter (APF) to direct the pulsating power into another energy-storage component. The main dc link filter capacitor can then be reduced substantially. Based on a mainstream dc APF topology, this paper proposed a new control strategy incorporating both dual-loop control and repetitive control. The circuit parameter design is also re-examined from a control point of view. The proposed APF scheme has better control performance, and is more suited for high power applications since it works in CCM and with a low switching frequency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.435-436
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• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• 한국전자파학회논문지
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• 제26권5호
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• pp.463-470
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• 2015

본 논문은 SIR 구조의 피드라인과 공진기를 이용한 새로운 구조의 마이크로스트립 이중대역 대역통과여파기(BPF)를 제안한다. SIR 구조의 피드라인을 이용하여 이중대역 BPF의 두 통과대역 각각에서 입력과 출력 피드라인의 자기장 최대 지점을 서로 일치시켜 공진기와 피드라인 사이의 결합을 최대화하여 여파기 손실을 감소시켰다. 또한, 이중대역 BPF의 제1통과대역 공진기에도 SIR 구조를 적용하여 1) 두 통과대역 사이의 저지대역 특성을 개선시키고, 2) 제2통과대역 공진기와의 결합을 최소화시켜 공진기 간격을 감소시켜 소형화에 기여하였다. 이렇게 하여 이중대역 BPF 통과대역의 중심주파수와 대역폭을 독립적으로 변경시키는 것은 물론, 필터링 성능을 개선하였다. WLAN 규격을 만족하는 이중대역 BPF를 제작하고, 측정 결과와 비교하여 제안한 여파기 설계 방법이 유용하다는 것을 입증하였다.

• 대한전자공학회논문지SD
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• 제47권11호
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• pp.13-22
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• 2010

본 논문은 입력 클록의 고주파 위상 잡음 억제와 정확한 듀티 사이클을 갖는 체배 주파수 생성을 위하여 Voltage-Controlled Oscillator(VCO)/Voltage-Controlled Delay Line(VCDL) 혼용기반의 다중 위상 Delay-Locked Loop(DLL)를 제시한다. 이 제안된 구조에서, 다중 위상 DLL은 혼용 VCO/VCDL의 입력 단에 nMOS 소스 결합 회로 기반의 이중 입력 차동 버퍼를 사용한다. 이것은 고주파 입력 위상 잡음 억제를 위하여 전 대역 통과 필터 특성을 갖는 기존 DLL의 입/출력 위상 전달을 저주파 통과 필터 특성을 갖는 PLL의 입/출력 위상 전달로 쉽게 변환시킬 수 있다. 또한, 제안된 DLL은 추가적인 보정 제어 루프 없이 단지 듀티 사이클 보정 회로와 위상 추적 루프를 이용하여 체배 주파수의 듀티 사이클 에러를 보정할 수 있다. $0.18{\mu}m$ CMOS 공정을 이용한 시뮬레이션 결과에서, 제안된 DLL의 출력 위상 잡음은 800MHz의 입력 위상 잡음을 갖는 1GHz 입력 클록에 대하여 -13dB 이하로 개선된다. 또한, 40%~60%의 듀티 사이클 에러를 갖는 1GHz 동작 주파수에서, 체배 주파수의 듀티 사이클 에러는 2GHz 체배 주파수에서 $50{\pm}1%$이하로 보정된다.