• Journal of Internet Computing and Services
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• v.22 no.3
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• pp.37-43
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• 2021

In this paper, we study how objects from front and back cameras can be recognized in real time in a mobile environment to segment regions of object pixels and synthesize them through image processing. To this work, we applied DeepLabV3 machine learning model to dual cameras provided by Apple's iOS. We also propose methods using Core Image and Core Graphics libraries from Apple for image synthesis and postprocessing. Furthermore, we improved CPU usage than previous works and compared the throughput rates and results of Depth and DeepLabV3. Finally, We also developed a camera application using these two methods.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.46-49
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• 2011

This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.145-146
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• 2011

In this paper, a bridgeless flyback power factor correction (PFC) rectifier which uses single magnetic core is proposed. The proposed PFC rectifiers utilize bidirectional switch to handle both positive and negative input voltage without bridge diodes. A transformer with dual output windings enables the rectifier dispense with any additional magnetic component. The operation of the proposed flyback PFC rectifier is analyzed, and its higher efficiency than its conventional counterpart is verified by experiment.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.5
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• pp.263-266
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• 2006

An optical microphone was developed using a dual-core multi-mode fiber block and a membrane type micromirror. The fiber block serves as a compact optical head, and the micromirror as a reflective diaphragm. The micromirror is designed to be suspended through a silicon bar connected t a frame, allowing for displacement induced by acoustic waves. The optical head is implemented by integrating two multi-mode fibers in a single block, and used to transfer light signals between it and the diaphragm. For the assembled microphone, its static characteristics were observed to reveal the operating point defined as the optimum distance between the optical head and the diaphragm. And its dynamic response was tested to exhibit a frequency bandwidth of 3 kHz with the variation of $\sim5dB$.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.3
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• pp.117-124
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• 2007

In order to operate CD and DVD compatibly in a pickup system, the objective lens comprise diffractive optical element(DOE) zone and aspheric curvature on its lens surface. The DOE objective lens is effective to simplify this dual-purpose pickup system of the 655nm and 785nm wavelength by using only one lens, but requires more precision manufacturing process and system due to the complicated shape. This paper presents the overall manufacturing process of this objective lens and describes main parameters in each process, for the correction of the aspheric surface in its core, the shrinkage compensation after injection molding, and the uniformity compensation by adjusting molding conditions.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.10a
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• pp.159-160
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• 2004

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.5
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• pp.2267-2285
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• 2016

Information Centric Networking that uses content name instead of IP address as routing identifier can handle challenges such as traffic explosion and user mobility, but it also suffers from scalability and incompatibility problems. In this paper by combining the concept of software defined networking and Internet end to end arguments, we propose a wide area deployable software defined information centric networking service model named SD-ICN. SD-ICN employs a dual space structure that separates edge service network and core transmission network. The enhanced SDN techniques are used in edge service network in order to implement intelligent data routing and caching, while traditional IP technique is reserved in core transmission network so as to provide wide area high speed data transmission. Besides, a distributed name resolution system based on the cooperation of different controllers is also presented. The prototype experiments in our campus network show that SD-ICN can be deployed in a scalable and incremental way with no modification of the core network, and can support typical communication modes such as multicast, mobility, multihoming, load balancing, and multipath data transmission effectively.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• Journal of the Korea Safety Management & Science
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• v.11 no.4
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• pp.161-168
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• 2009

Ubiquitous application is in need of high-level technology to meet various requests for ubiquitous service. In order to adopt ubiquitous technology in not only pilot projects but also regional services, many projects like u-City are implemented in and outside the country. RFID has been known as one of the important technology to provide with core benefits of Ubiquitous services. Because each band of RFID technology has merits and demerits concurrently, single-band RFID system has limitations for various RFID services. Thus, we developed dual-band RFID system enable to provide with 13.56MHz and 2.45GHz RFID service at the same time to compensate the shortage of single-band RFID system. Also we have considered the way that the firmware would control signals without collision, studied battery life and range for tag, and made hardware for dual-band RFID service.

• Journal of Power Electronics
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• v.12 no.6
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.