• 한국정보전자통신기술학회논문지
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• 제15권4호
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• pp.291-297
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• 2022

본 논문은 가전용 교류 전동기 구동을 위한 인버터 회로에 포함된 지능형 스위칭 모듈인 IPM 모듈에 대한 특성 및 신뢰성 계측 회로 설계 방법에 대한 연구이다. IPM은 전동기 구동기의 핵심 부품으로 그 스위칭 특성이 서보 구동 중에 일관되게 유지돼야 한다. 그 특성 중 스위치 온 특성을 결정하는 콜렉터-에미터간 도통 전압 Vce(on) 특성이 중요하다. 인버터 구성의 핵심 부품인 IPM은 여러 브랜드의 제품이 생산되고 있기 때문에 응용시스템의 최적 성능을 위해서는 IPM의 제품군에 따른 IGBT 스위치의 콜렉터-에미터간 도통 전압 Vce(on) 값을 측정하기 위한 방법 및 계측 평가 시스템이 필요하다. 제안된 방법은 제조사별 IPM이 전동기 구동회로에 장착된 상태에서 부하에 따른 Vce(on) 값을 계측 평가할 수 있는 새로운 방법으로 사용자 회사 입장에서는 중요한 설비가 될 수 있다.

• 센서학회지
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• 제23권2호
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1286-1288
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• 1994

Methods are described for the design and fabrication of the sensor circuits on the polarographic oxygen sensing electrodes. The discussion includes: a method for the +5V single-supply driving for the sensor circuits, a method of low power comsumption for the front-end electronics. Typical polarograms for the commercial DO probes using this sensor circuits are presented. High accuracy of the I to V conversion using the circuits is verified.

• Journal of Information Display
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• 제9권4호
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• pp.45-49
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• 2008

The characteristics of the sustain-driving circuit were examined in this paper. The sustain-driving circuit is in charge of the most important part of PDP driving because it manages most of the power consumption in the PDP. A couple of gatedriving circuits for the sustain-driving circuit were introduced in this paper, and a new driving circuit was also proposed. This new circuit is more cost-effective and has a simpler PCB layout compared to the conventional one. Some additional driving advantages were noted as well.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.837-840
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• 2007

We propose a novel digital driving method for AM-OLED (Active Matrix-Organic Light Emitting Diode) display. Proposed method modulates $V_{DD}$ so that luminance may be weighted in accordance with the bit significance. We can increase the minimum emission time or slower scan circuits are applicable by using proposed method.

• 전자공학회논문지C
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• 제35C권4호
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.462-470
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• 2015

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

• Journal of Electrical Engineering and Technology
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• 제7권4호
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• pp.538-545
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• 2012

In this paper a novel cascaded transformer multilevel inverter is proposed. Each basic unit of the inverter includes two DC sources, single phase transformers and semiconductor switches. This inverter, which operates as symmetric and asymmetric, can output more number of voltage levels in the same number of the switching devices. Besides, the number of gate driving circuits is reduced, which leads to circuit size reduction and lower power consumption in the driving circuits. Moreover, several methods to determination of transformers turn ratio in proposed inverter are presented. Theoretical analysis, simulation results using MATLAB/SIMULINK and experimental results are provided to verify the operation of the suggested inverter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1442-1444
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• 2001

A new low-temperature poly-Si TFT employing a counter-doped lateral body terminal is proposed and fabricated, in order to enhance the stability of poly-Si TFT driving circuits. The LBT structure effectively suppresses the kink effect by collecting the counter-polarity carriers and suppresses the hot carrier effect by reducing the peak lateral field at the drain junction. The proposed device is immune to dynamic stress, so that it is suitable for low voltage and high speed driving circuits of AMLCD.

• 대한전자공학회논문지
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• 제15권4호
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• pp.7-13
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• 1978

쉬프트레지스터 (SR) 모듈을 기억소자로서 사용하여 순서회로를 실현하는 방법을 논하였다. 종래의 방법은 특수한 조건하에서 SR를 선택하는 것으로서 그것을 구동하는 조합논리회로의 복잡도는 고려되지 않았다. 본 논문은 한 정수치함수를 사용하여 단수가 최소인 SR를 선택하였고 각 SR를 구동하는 조합논리회로의 입력선수를 비교하여 논리회로의 복잡도가 낮은 최적 상태할당을 구하였다.