• Title/Summary/Keyword: Driver circuit

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a-Si TFT Integrated Gate Driver Using Multi-thread Driving

  • Jang, Yong-Ho;Yoon, Soo-Young;Park, Kwon-Shik;Kim, Hae-Yeol;Kim, Binn;Chun, Min-Doo;Cho, Hyung-Nyuck;Choi, Seung-Chan;Moon, Tae-Woong;Ryoo, Chang-Il;Cho, Nam-Wook;Jo, Sung-Hak;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1251-1254
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    • 2006
  • A novel a-Si TFT integrated gate driver circuit using multi-thread driving has been developed. The circuit consists of two independent shift registers alternating between the two mode, "wake" and "sleep". The degradation of the circuit is retarded since the bias stress is removed during the sleep mode. It has been successfully integrated in 14.1-in. XGA LCD Panel, showing enhanced stability.

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Design of the Driver IC for 500 V Half-bridge Converter using Single Ended Level Shifter with Large Noise Immunity (잡음 내성이 큰 단일 출력 레벨 쉬프터를 이용한 500 V 하프브리지 컨버터용 구동 IC 설계)

  • Park, Hyun-Il;Song, Ki-Nam;Lee, Yong-An;Kim, Hyoung-Woo;Kim, Ki-Hyun;Seo, Kil-Soo;Han, Seok-Bung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.8
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    • pp.719-726
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    • 2008
  • In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.

Self-Feeder Driver for Voltage Balance in Series-Connected IGBT Associations

  • Guerrero-Guerrero, A.F.;Ustariz-Farfan, A.J.;Tacca, H.E.;Cano-Plata, E.A.
    • Journal of Power Electronics
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    • v.19 no.1
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    • pp.68-78
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    • 2019
  • The emergence of high voltage conversion applications has resulted in a trend of using semiconductor device series associations. Series associations allow for operation at blocking voltages, which are higher than the nominal voltage for each of the semiconductor devices. The main challenge with these topologies is finding a way to guarantee the voltage balance between devices in both blocking and switching transients. Most of the methods that have been proposed to mitigate static and dynamic voltage unbalances result in increased losses within the device. This paper introduces a new series stack topology, where the voltage unbalances are reduced. This in turn, mitigates the switching losses. The proposed topology consists of a circuit that ensures the soft switching of each device, and one auxiliary circuit that allows for switching energy recovery. The principle for the topology operation is presented and experimental tests are performed for two modules. The topology performs excellently for switching transients on each of the devices. The voltage static unbalances were limited to 10%, while the activation/deactivation delay introduced by the lower module IGBT driver takes place in the dynamic unbalances. Thus, the switching losses are reduced by 40%, when compared to hard switching configurations.

The TROPHY (Talented Role-playing Technology with a Dual Polarity Sustainer in Hybrid Mono Board) Driving Method

  • Park, Chang-Joon;Kwak, Jong-Woon;Kim, Tae-Hyung;Park, Hyun-Il;Moon, Seong-Hak
    • Journal of Information Display
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    • v.7 no.4
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    • pp.24-26
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    • 2006
  • We have developed a new driving method named TROPHY(Talented Role-playing Technology with Dual Polarity sustainer in Hybrid Mono board). In this method, the sustain voltage is partially compared to the conventional method and the number of power sources is reduced by voltage level unification during the reset, address and sustain period. The hybrid mono board was especially developed to implement those technologies. Through this, we can lower the cost with the TROPHY compared to the conventional one. It is a suitable technology to improve the reliability of circuit and image sticking problem. We can also reduce the number of driving boards and the EMI problem compared with those of the conventional method.

Design of Calibration Circuit for LCOS Microdisplay (LCOS 마이크로디스플레이 구동용 보정회로 설계)

  • Lee, Youn-Sung;Wee, Jung-Wook;Han, Chung-Woo;Song, Nam-Chol
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.10a
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    • pp.469-471
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    • 2022
  • This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

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Development of a New Hybrid Silicon Thin-Film Transistor Fabrication Process

  • Cho, Sung-Haeng;Choi, Yong-Mo;Kim, Hyung-Jun;Jeong, Yu-Gwang;Jeong, Chang-Oh;Kim, Shi-Yul
    • Journal of Information Display
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    • v.10 no.1
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    • pp.33-36
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    • 2009
  • A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit

A Novel Energy Recovery Circuit for AC PDPs with Reduced Sustain Voltage (새로운 유지구동전압 저감형 AC PDP용 에너지 회수회로)

  • Lim, Seung-Bum;Hong, Soon-Chan
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.6
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    • pp.494-501
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    • 2006
  • In this paper, a novel energy recovery circuit for AC PDPs(Plasma Display Panels) with reduced sustain voltage is proposed to improve the performance of conventional circuits such as TERES(TEchnology of REciprocal Sustainer). In the TERES circuit, the sustain voltage is the half of general sustaining driver for AC PDPs, however, there is no energy recovery circuit. In the proposed circuit, the efficiency is heightened by installing in energy recovery circuit and the loss of switching device is reduced by performing the zero voltage switching or zero current switching. Although the energy recovery circuit is added, the number of active switching elements of the proposed circuit is the same as that of the TERES circuit. The operations of the proposed circuit are analyzed for each mode and its validity is verified by the simulations and experimentation.

A Design of Gate Driver Circuits in DMPPT Control for Photovoltaic System (태양광 분산형 최대전력점 추적 제어를 위한 고전압 게이트 드라이버 설계)

  • Kim, Min-Ki;Lim, Shin-Il
    • Journal of Korea Society of Industrial Information Systems
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    • v.19 no.3
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    • pp.25-30
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    • 2014
  • This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

Design of A 1'${\times}$1', 512${\times}$512 Poly-Si TFT-LCD with Integrated 8-bit Parallel-Serial Digital Data Drivers

  • Shin, Won-Chul;Lee, Seung-Woo;Chung, Hoon-Ju;Han, Chul-Hi
    • Journal of Information Display
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    • v.2 no.2
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    • pp.1-6
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    • 2001
  • A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

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