• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• Publications of The Korean Astronomical Society
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• v.11 no.1
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• pp.109-123
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• 1996

We have developed a 5GHz continuum receiver system. The receiver is a direct type receiver. In order to reduce the noise due to the fluctuation of the gain in the amplifiers, the system employs the Dicke switching method. We made the 5GHz low-noise amplifier and the bandpass filter. The low-noise amplifier gives ${\sim}35dB$ gain and has ${\sim}210K$ noise temperature. The bandpass filter has a passband between 4.3 and 5.4GHz. We also made switch driver, video amplifiers, phase detector, and integrator. Using a 1.8 meter offset parabolic antenna, we measured the efficiency of the system. Since the antenna does not have a driver to track objects, observations were performed with the antenna fixed. The measured noise temperature of the system is ${\sim}650K$. From the observation of the blank sky, noise level was measured. It was found that the systematic noise(${\sim}0.5K$: peak to peak value) is much larger than the thermal noise. The systematic noise is possibly related to the stability of the DC power supplied to the receiver system. Besides the noise of the system, it was found that the airplanes are the very serious noise sources. We measured the radio flux of the Sun using the developed system. The observed radio flux of the Sun is ${\sim}10^6Jy$, which is close to the known value of the quiet Sun. The test observation of the Sun shows that the angular beam size of the antenna is ${\sim}2.2^{\circ}$.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.1-5
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• 2012

This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-${\mu}m$ by 200-${\mu}m$ optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-$mm^2$ area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only $120{\mu}W$ in the sleep mode.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.553-554
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• 2006

In this paper, 77 GHz CPW power amplifier MMIC, which are consisted of a 2 stage driver stage and a power stage employing $8{\times}50um$ gate width, have been successfully developed by using 120nm $In_{0.4}AlAs/In_{0.35}GaAs$ Metamorphic high electron mobility transistors (MHEMTs). The devices show an extrinsic transconductance $g_m$ of 660 mS/mm, a maximum drain current of 700 mA/mm, and a gate drain breakdown voltage of -8.5 V. A cut-off frequency ($f_T$) of 172 GHz and a maximum oscillation frequency ($f_{max}$) of over 300 GHz are achieved. The fabricated PA exhibited high power gain of 20dB only with 3 stages. The output power is measured to be 12.5 dBm.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1079-1086
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• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.109-109
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• 2009

This paper represented driving characteristic of a thin-type ultrasonic motor by fabricating and utilizing two kinds of drivers which could generate sinusoidal wave, square wave, respectively. A thin brass plate was used as a cross shaped vibrator and sixteen ceramic plates were attached on upper and bottom side of the brass plate. From the thin stator, elliptical displacements of the four contact tips were obtained. Speed, torque, and current were measured by applying sinusoidal waves through driving equipment such as function generator, power amplifier: to measure characteristic of the motor. As a result, the speed and the torque changed linearly at either driving frequency of 88.6 ~ 87.6[kHz] or voltage of 24~36[V]. Two-drivers which generate sinusoidal waves and square waves were designed respectively, and then were compared through some experiments in order to be put to practical use. In conclusion, the drivers had similar characteristic of speed-torque at similar frequency and voltage. It was able to control the motor linearly by using the driver generating square wave among two-drivers. Besides, it also was possible to make the drivers smaller.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.9
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• pp.34-40
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• 1999

In order to establish the design technique of the robust current controller in d.c series wound motor driver system, this paper proposes a method of the compensated Bang-Bang current control using d.c series wound motor driver system under the improperly variable load to get minimum time for the torque control. The compensated Bang-Bang current controller structure is simpler than that of PID plus Bang-Bang controller. This paper shows that a general 16 bits microprocessor is efficiently used to implement such an algorithm. The calculation time of software is extremely small when compared with that of conventional PID plus Bang-Bang controller. Both nonlinear operating characteristics of digital switching elements and describing function methods are used for the analysis and synthesis. Real-time implementation of the compensated Bang-Bang current controller is achieved. The concept of design strategy of the control and the PWM waveform generation algorithms are presented in this paper.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.