• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.10
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• pp.741-747
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• 1987

The high-power Nd:glass system with five-stage amplifier was designed and its amplification characteristics was studied for developing high-power Nd:glass laser system as an energy driver of inertial confinement fusion(ICF). In order to study the amplification characteristics of remporal and spacial Gaussian laser beam, the dependence of them on pumping efficiency and rod loss were studied and discussed. The output energy of this system using phosphate Nd glass rod(LHG-7,LHG-8) and silicate Nd glass rod(LSG-91H), respectively, was calculated by the computer simulation using Avizonis-Grotbeck and Frantz Nodvik equations. As results of this simulation, it was found that the shorter the risetime of laser pulse, the larger the amplification factor and that the larger peak value of laser pulse, the lower the amplification factor. The output inergies of 179J, 344J, and 7J were obtained by the designed five-stage amplified high-power Nd:glass laser system using glass rods of LHG-7,LHG-8, and LSG-91H, respectively. From the results it was found that the laser system using the LHG-8 glass rod was the most excellent one among the systems and the cross section for stimulated emission of the gain coefficient was essentially important parameter for the amplification characteristics.

• ETRI Journal
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• v.34 no.5
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• pp.649-654
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• 2012

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.3
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• Journal of Korean Port Research
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• v.11 no.2
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• pp.273-280
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• 1997

Recently the importance of the cargo handling equipments in a port has been increasing to get strong competition from other ports. Many ports are making efforts to modernize their cargo handling equipments. The kernel technology of such equipments is the speed control of DC motor which is used as an essential part of them. In this paper, we discuss the speed control of a DC motor as a basic work for building cargo handling equipments in a port. DC Motors are still widely used in industrial fields, as driving power motor for electrical fields. DC drives, being easy to control, are widely used in many variable-speed and position control drive system. Traditional analog control circuits used in such applications have many disadvantages. Complex control schemes are difficult to implement with analog components. All these factor and invention of the microprocessor has made it possible to use digital control circuits, using microprocessing system. These digital circuits have been found to be reliable, flexible, and also immune to noise. In this paper it presents the speed control of a SCR DC motor driver which using dual converter by 80c196kc microprocessor. We developed a thyristor power amplifier which does not cause damage thyristor because it is designed to prevent triggering the two SCRs in the same arm simultaneously. And it was analyzed voltage and currents wave at reactive load.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.161-165
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• 2023

This paper designed a voltage feedback driving circuit to compensate for the characteristic deviation of the Active Matrix Organic Light Emitting Diode driving Thin Film Transistor. This paper describes a stable and fast circuit by applying charge sharing and polar stabilization methods. A 12-inch Organic Light Emitting Diode with a Double Wide Ultra eXtended Graphics Array resolution creates a screen distortion problem for line parasitism, and charge sharing and polar stabilization structures were applied to solve the problem. By applying Charge Sharing, all data lines are shorted at the same time and quickly positioned as the average voltage to advance the compensated change time of the gate voltage in the next operation period. A buffer circuit and a current pass circuit were added to lower the Amplifier resistance connected to the line as a polar stabilization method. The advantage of suppressing the Ringing of the driving Thin Film Transistor can be obtained by increasing the stability. As a result, a circuit was designed to supply a stable current to the Organic Light Emitting Diode even if the characteristic deviation of the driving Thin Film Transistor occurs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.352-361
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• 2010

In this paper, a compact 20 W block-up-converter for C-band satellite communication is designed and implemented. The designed block up-converter consists of an intermediate frequency circuit, a mixer and local oscillator, a driver amplifier, a solid-state power amplifier, waveguide circuits, and a power supply module. To reduce the size of the block-up-converter, all circuits are assembled within an housing, so its dimension is just $21{\times}14{\times}11cm^3$. Especially, the waveguide filter and microstirp-to-waveguide transition are easily implemented using an housing. Also, to meet spurious and harmonics specification, various compact microstrip filters including an elliptic filter are integrated. Measurement results show that the developed block up-converter has good electrical performances: the output power of 43.7 dBm, the minimum gain of 65 dB, the gain flatness of ${\pm}1.84$, the IMD3 of -35 dBc, and the harmonic level of -105 dBc.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.132-137
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• 2003

This performance is motivated to develop a tracking antenna system for receive the satellite broadcasting signal in the coast sailing ship. Therefore, this system is made to small size, light weight and simple operation which is must to low cost system for popularization of small size ship and adaptive possibilities with useful on a ship in the coast using 1 axis Az-mount. The antenna mount structure is a compact size and easy operation to the Az-axis type which is operated by step motor. The antenna unit is a domestic made plate type of patch array and ship's moving detection is using the gyro sensor for ship's moving control. We are designed to algorithm, which walking is abreast for step track and ship's moving compensation. Ship's moving compensation is adapted to the closed loop control method by detection from gyro sensor. This system is consisted of micro processor, ADC, comparative amplifier, step motor driver, mount mechanism and algorithm. We have analysised the tracking performance of prototype on sailing ship board.

• Journal of Radiation Protection and Research
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• v.41 no.2
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• pp.81-86
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• 2016

Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.