• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국통신학회논문지
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• 제3권1호
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• pp.18-25
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• 1978

반도체 소자에서 생기는 1/f 형의 잡음의 근원이 무엇인가에 대해 지금까지 여러 이론이 나왔다. 그중에도 Mcwhorter's Surface model이 대표적인 이론이었다. 그러나 Hooge는 이론에 반기를 들고 나왔다. Hooge의 이론에 의하면 thermo cell이나 Concentration cell에서의 1/f-형의 잡음이 표면효과(surface effect)가 아니라는 것이다. 본 논문에서는 이 두 대표적인 이론을 종합검토할 수 있는 Langenvin type의 Boltzmann transport equation에 입각하여 새로운 일반이론을 세웠다. 본 논문에서는 N형 채널을 갖고 있는 금속산화물반도체 전계효과 트랜지스터에서 단일준의 Shockley-Read-Hall recombination center에 의한 단락회로에서 드레인의 1/f-형 잡음스펙트럼을 계산하기 위해 시간에 따라 변화하는 양을 포함시키므로써 각 에너지대의 케리어에 대해 준-페르미준위를 정의할 수 없다고 가정했으므로, 1/f-형의 잡음은 다수케리어 효과에 기인한다고 가정했다. 이러한 가정하에서 유도된 1/f-형의 잡음은 금속산화물반도체 전계효과 트랜지스터에서 1/f-형의 잡음에 중요한 요인들을 모두 보여주었다. : 적주파에서 플렛티유를 나타내지 않았고 채널의 면적 A와 드레인 바이어스 전압 V에 비례하고 체널의 길이 L에 반비례한다. 본 논문의 모델에서는 1/f-응답에서 1/f2에 대한 잡음스트럼의 전이주파수와 P-n 합다이오우드의 surfact center에 관계되는 완화시간(relaxation time)에 대응하는 주파수 사이를 구별하여 설명할 수 있었다. 본 논문의 결과에서 1/f-형 잡음스펙트럼은 격자산란이 주원인이 된다. 금속산화물반도체 전계효과 트랜지스터를 살펴보면 격자산란이 주로 표면에서 일어나기 때문에 1/f-형 잡음이 표면효과라고 말할 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.679-682
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• 2005

Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

• 설비공학논문집
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• 제26권12호
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• pp.605-619
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• 2014

This article reviews the papers published in the Korean Journal of Air-Conditioning and Refrigeration Engineering during 2013. It is intended to understand the status of current research in the areas of heating, cooling, ventilation, sanitation, and indoor environments of buildings and plant facilities. Conclusions are as follows. (1) The research works on the thermal and fluid engineering have been reviewed as groups of fluid machinery, pipes and relative parts including orifices, dampers and ducts, fuel cells and power plants, cooling and air-conditioning, heat and mass transfer, two phase flow, and the flow around buildings and structures. Research issues dealing with home appliances, flows around buildings, nuclear power plant, and manufacturing processes are newly added in thermal and fluid engineering research area. (2) Research works on heat transfer area have been reviewed in the categories of heat transfer characteristics, pool boiling and condensing heat transfer and industrial heat exchangers. Researches on heat transfer characteristics included the results for general analytical model for desiccant wheels, the effects of water absorption on the thermal conductivity of insulation materials, thermal properties of Octadecane/xGnP shape-stabilized phase change materials and $CO_2$ and $CO_2$-Hydrate mixture, effect of ground source heat pump system, the heat flux meter location for the performance test of a refrigerator vacuum insulation panel, a parallel flow evaporator for a heat pump dryer, the condensation risk assessment of vacuum multi-layer glass and triple glass, optimization of a forced convection type PCM refrigeration module, surface temperature sensor using fluorescent nanoporous thin film. In the area of pool boiling and condensing heat transfer, researches on ammonia inside horizontal smooth small tube, R1234yf on various enhanced surfaces, HFC32/HFC152a on a plain surface, spray cooling up to critical heat flux on a low-fin enhanced surface were actively carried out. In the area of industrial heat exchangers, researches on a fin tube type adsorber, the mass-transfer kinetics of a fin-tube-type adsorption bed, fin-and-tube heat exchangers having sine wave fins and oval tubes, louvered fin heat exchanger were performed. (3) In the field of refrigeration, studies are categorized into three groups namely refrigeration cycle, refrigerant and modeling and control. In the category of refrigeration cycle, studies were focused on the enhancement or optimization of experimental or commercial systems including a R410a VRF(Various Refrigerant Flow) heat pump, a R134a 2-stage screw heat pump and a R134a double-heat source automotive air-conditioner system. In the category of refrigerant, studies were carried out for the application of alternative refrigerants or refrigeration technologies including $CO_2$ water heaters, a R1234yf automotive air-conditioner, a R436b water cooler and a thermoelectric refrigerator. In the category of modeling and control, theoretical and experimental studies were carried out to predict the performance of various thermal and control systems including the long-term energy analysis of a geo-thermal heat pump system coupled to cast-in-place energy piles, the dynamic simulation of a water heater-coupled hybrid heat pump and the numerical simulation of an integral optimum regulating controller for a system heat pump. (4) In building mechanical system research fields, twenty one studies were conducted to achieve effective design of the mechanical systems, and also to maximize the energy efficiency of buildings. The topics of the studies included heating and cooling, HVAC system, ventilation, and renewable energies in the buildings. Proposed designs, performance tests using numerical methods and experiments provide useful information and key data which can improve the energy efficiency of the buildings. (5) The field of architectural environment is mostly focused on indoor environment and building energy. The main researches of indoor environment are related to infiltration, ventilation, leak flow and airtightness performance in residential building. The subjects of building energy are worked on energy saving, operation method and optimum operation of building energy systems. The remained studies are related to the special facility such as cleanroom, internet data center and biosafety laboratory. water supply and drain system, defining standard input variables of BIM (Building Information Modeling) for facility management system, estimating capability and providing operation guidelines of subway station as shelter for refuge and evaluation of pollutant emissions from furniture-like products.

• 대한전자공학회논문지SD
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• 제48권6호
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• pp.1-6
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• 2011

투명 산화물 반도체 (Transparent Oxide-TFT)를 활성층과 소스/드레인, 게이트 전극층으로 동시에 사용한 비결정 indium zinc oxide (a-IZO), 절연층으로 co-sputtered $HfO_2-Al_2O_3$ (HfAIO)을 적용하여 실온에서 RF-magnetron 스퍼터 공정에 의해 제작하였다. TFT의 게이트 절연막으로써 $HfO_2$ 는 그 높은 유전상수( > 20)에도 불구하고 미세결정구조와 작은 에너지 밴드갭 (5.31eV) 으로 부터 기인한 거친계면특성, 높은 누설전류의 단점을 가지고 있다. 본 연구에서는, 어떠한 추가적인 열처리 공정 없이 co-sputtering에 의해 $HfO_2$와 $Al_2O_3$를 동시에 증착함으로써 구조적, 전기적 특성이 TFT 의 절연막으로 더욱 적합하게 향상되어진 $HfO_2$ 박막의 변화를 x-ray diffraction (XRD), atomic force microscopy (AFM) and spectroscopic ellipsometer (SE)를 통해 분석하였다. XRD 분석은 기존 $HfO_2$ 의 미세결정 구조가 $Al_2O_3$와의 co-sputter에 의해 비결정 구조로 변한 것을 확인 시켜 주었고, AFM 분석을 통해 $HfO_2$ 의 표면 거칠기를 비교할 수 있는 RMS 값이 2.979 nm 인 것에 반해 HfAIO의 경우 0.490 nm로 향상된 것을 확인하였다. 또한 SE 분석을 통해 $HfO_2$ 의 에너지 밴드 갭 5.17 eV 이 HfAIO 의 에너지 밴드 갭 5.42 eV 로 향상 되어진 것을 알 수 있었다. 자유 전자 농도와 그에 따른 비저항도를 적절하게 조절한 활성층/전극층 으로써의 IZO 물질과 게이트 절연층으로써 co-sputtered HfAIO를 적용하여 제작한 Oxide-TFT 의 전기적 특성은 이동도 $10cm^2/V{\cdot}s$이상, 문턱전압 2 V 이하, 전류점멸비 $10^5$ 이상, 최대 전류량 2 mA 이상을 보여주었다.

• 대한전자공학회논문지SD
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• 제43권3호
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• pp.21-32
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• 2006

본 논문에서는 누설전력 소비뿐만 아니라 스위칭 전력 소비를 동시에 줄일 수 있는 새로운 저전력 SRAM 회로를 제안한다. 제안된 저전력 SRAM은 대기모드와 쓰기동작에서는 셀의 소스라인 전압을 $V_{SSH}$로 증가시키고 읽기동작에서만 소스라인 전압을 다시 $V_{SS}$가 되도록 동적으로 조절한다. SRAM 셀의 소스라인 전압을 동적으로 조절하면 reverse body-bias 효과, DIBL 효과, 음의 $V_{GS}$ 효과를 이용하여 셀 어레이의 누설전류를 1/100 까지 감소시킬 수 있다. 또한 누설전류를 억제하기 위해 사용된 소스라인 드라이버를 이용하여 SRAM의 쓰기동작에서 비트라인 전압의 스윙 폭을 $V_{DD}-to-V_{SSH}$로 감소시킴으로써 SRAM의 write power를 대폭 감소시킬 수 있고 쓰기동작 중에 있는 셀들의 누설 전류 소비도 동시에 줄일 수 있다. 이를 위해 새로운 write driver를 사용하여 low-swing 쓰기동작 시 성능 감소를 최소화하였다. 누설전력 소비 감소 기법과 스위칭 전력 소비 감소 기법을 동시에 사용함으로써 제안된 SRAM은 특히 미래의 큰 누설전류가 예상되는 70-nm 이하 급 초미세 공정에서 유용할 것으로 예측된다. 70-nm 공정 파라미터를 이용해서 시뮬레이션한 결과 누설전력 소비의 93%와 스위칭 전력 소비의 43%를 줄일 수 있을 것으로 보인다. 본 논문에서 제안된 저전력 SRAM의 유용성과 신뢰성을 검증하기 위해서 $0.35-{\mu}m$ CMOS 공정에서 32x128 bit SRAM이 제작 및 측정되었다. 측정 결과 기존의 SRAM에 비해 스위칭 전력이 30% 적게 소비됨을 확인하였고 사용된 메탈 차폐 레이어로 인해서 $V_{DD}-to-V_{SSH}$ 전압이 약 1.1V 일 때까지 오류 없이 동작함을 관측하였다. 본 논문의 SRAM 스위칭 전력감소는 I/O의 bit width가 증가하면 더욱 더 중요해질 것으로 예상할 수 있다.