• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1995.05a
• /
• pp.43-46
• /
• 1995

We fabricate a bottom gate a-Si:H TFT on N-Type <100> Si wafer. According to the variation of gate and drain voltage, the hysteresis characteristic curves were measured experimentally. Also, we showed that the model predict the hysteresis characteristic successfully. Drain current on the hysteresis characteristic currie showed an exponential variation. Hysteresis area of TFT increased with the drain voltage increase and decreases with the drain voltage decrease.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.309-312
• /
• 2003

In this study, the electrical characteristic of Symmetric high voltage MOSFET (SHVMOSFET) for display driver IC were investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length. In high temperature condition(>400K), drain current decreased over 20％, and specific on-resistance increased over 30％ in comparison with room temperature.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.43 no.7
• /
• pp.1135-1143
• /
• 1994

We fabricate a bottom gate a-Si:H TFT on N-Type <100> Si wafer. According to the Variation of gate and drain voltage, the hysteresis characteristic curves were measured experimentally. Also, we proposed model equation and showed that the model predict the hysteresis characteristic successfully. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the drain voltage increase and decreases with the drain voltage decrease.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.7A
• /
• pp.451-466
• /
• 2003

Untethered nodes in mobile ad-hoc networks strongly depend on the efficient use of their batteries. In this paper, we propose a new metric, the drain rate, to forecast the lifetime of nodes according to current traffic conditions. This metric is combined with the value of the remaining battery capacity to determine which nodes can be part of an active route. We describe new route selection mechanisms for MANET routing protocols, which we call the Minimum Drain Rate (MDR) and the Conditional Minimum Drain Rate (CMDR). MDR extends nodal battery life and the duration of paths, while CMDR also minimizes the total transmission power consumed per packet. Using the ns-2 simulator and the dynamic source routing (DSR) protocol, we compare MDR and CMDR against prior proposals for power-aware routing and show that using the drain rate for power-aware route selection offers superior performance results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.1
• /
• pp.74-80
• /
• 1990

The transconductance of short channel LDD MOSFETs in the saturation region (high Vd)has shown different characteristics from that of conventional device. The transconductance in saturation regime of short channel LDD MOSFETs is reduced from maximum value at higher gate voltage. This decline is analyzed as the velocity saturation effects of carrier at LDD region but accurate analytical expressions for the drain current Idsat and the transconductance Gmsat in the saturation regime are still not in existence. Recently the drain current dependence of parasitic source resistance Rs has been modeled from the velocity saturation of carriers in LDD region. In this study, we approximate that Rmsat that Rs is linearly dependent on the applied gate voltage. Analytical expressions for Idsat and Gmsat obtained from this approximation show the same general behavior as experimental results of short channel LDD NMOSFETs.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.12
• /
• pp.159-165
• /
• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.160-162
• /
• 2016

A compact model of tunnel field effect transistor (TFET) has been developed. The model includes a surface potentia calculation module and a band-to-band-tunneling current module. Model comparison with TCAD shows that the mode calculates TFET surface potential and drain current accurately.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.51 no.3
• /
• pp.134-140
• /
• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Proceedings of the Korea Society of Information Technology Applications Conference
• /
• 2005.11a
• /
• pp.99-102
• /
• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.43 no.6
• /
• pp.951-957
• /
• 1994

We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.