• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.345-352
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• 2017

In this paper, a non-dissipative snubber for reducing the switching losses in the step down converter is proposed. The conventional step down converter, e.g., buck converter, suffers from serious switching losses and consequentially heat generation because of its hard switching. Thus, it is unsuitable for high switching frequency operation. Reduction of the reactive components' size, such as an output inductor and capacitor, is difficult. The proposed snubber can slow down the increasing current slopes and switch voltage at turn-on and turn-off transients, thereby significantly reducing the switching loses. Additionally, the slowly increasing current during switch turn-on transition, can effectively solve the output rectifier diode reverse recovery problem. Therefore, the proposed non-dissipative snubber not only leads to the efficiency of converter operation at high switching frequency but also reduces the reactive components size in proportion to the switching frequency. To confirm the validity of the proposed circuit, theoretical analysis and experimental results from a 150 W, 1 MHz prototype are presented.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.801-807
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• 2012

In this paper, design and implementation of frequency down converter based on LC filter technic. Single frequency down converter, designed a low-noise amplifier, mixer, IF amplifier, LC filter was configured. And it is composed of DC block capacitors and RF bypass capacitor. LC filter, replace it with the IC reduced the power and realized low cost. The gain of single down converter is about 10dBm and realized by 18MHz bandwidth at 70MHz band.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• Journal of IKEEE
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• v.12 no.1
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• pp.34-42
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• 2008

This paper proposes a new on-chip voltage down converter(VDC), which employs a new reference voltage generator(RVG). The converter adopts a temperature-independence reference voltage generator, and a voltage-up converter. The architecture of the proposed VDC has a high-precision, and it was verified based on a 0.25${\mu}m$ 1P5M standard CMOS technology. For 2.5V to 1.0V conversion, the RVG circuit has a good characteristics such as temperature dependency of only 0.2mV/$^{\circ}C$, and the voltage-up circuit has a good voltage deviation within ${\pm}$0.12% for ${\pm}$5% variation of supply voltage VDD. The output voltage is stabilized with ${\pm}$1mV for load current varying from 0 to 100mA.

• Journal of Power Electronics
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• v.14 no.2
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• pp.203-216
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• 2014

In the conventional dc-dc converter, a pair of additional diode and the adjacent passive component capacitor/inductor can be added to the circuit with an X-shape connection, which generates a family of new topologies. The novel circuits, also called diode-assisted dc-dc converter, enhance the voltage boost/buck capability and have a great potential for high step-up/step-down power conversions. This paper mainly investigates and compares conventional dc-dc converter and diode-assisted dc-dc converter in wide range power conversion from the aspects of silicon devices, passive components requirements, electro-magnetic interference (EMI) and efficiency. Then, a comprehensive comparison example of a high step-up power conversion system was carried out. The two kinds of boost dc-dc converters operate under the same operation conditions. Mathematical analysis and experiment results verify that diode-assisted dc-dc converters are very promising for simultaneous high efficiency and high step-up/step-down power conversion in distributed power supply systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.555-558
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• 2009

This paper presents a step-down converter IC for automotive applications. This device was designed for a 40 V/1 A high-power output for voltage reference of automotive IC. It provides 250kHz PWM (pulse width modulation) and PFM(pulse frequency modulation) according to load conditions. This device was simulated spectre of IC-design-tools and fabricated Dong-bu Hitec 0.35um BD350BA process.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.641-644
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• 2021

Wearable devices and IoT are being utilized in various fields, where all systems are developing in the direction of multi-functionality, low power consumption, and high speed. In this paper, we propose a DC -DC Step-down C onverter for IoT smart devices. The proposed DC -DC Step-down converter is composed of a control block of the power supply stage. It also consists of an overheat protection circuit, under-voltage protection circuit, an overvoltage protection circuit, a soft start circuit, a reference voltage circuit, a lamp generator, an error amplifier, and a hysteresis comparator. The proposed DC-DC converter was designed and fabricated using a Magnachip / Hynix 180nm CMOS process, 1-poly 6-metal, the measured results showed a good match with the simulation results.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1445-1453
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• 2017

In this study, a new zero-voltage transition (ZVT) buck converter with coupled inductor using a synchronous rectifier and a lossless clamp circuit is proposed. The regular buck converter with tapped inductor has extended duty cycle for high step-down applications. However, the leakage inductance of the coupled inductor produced considerable voltage spikes across the switch. A lossless clamp circuit is used in the proposed converter to overcome this problem. The freewheeling diode was replaced with a synchronous rectifier to reduce conduction losses in the proposed converter. ZVT conditions at turn-on and turn-off instants were provided for the main switch. The synchronous rectifier switch turned on under zero-voltage switching, and the auxiliary switch turn-on and turn-off were under zero-current condition. Experimental results of a 100 W-100 kHz prototype are provided to justify the validity of the theoretical analysis. Moreover, the conducted electromagnetic interference of the proposed converter is measured and compared with its hard-switching counterpart.