• 제목/요약/키워드: Down converter

검색결과 353건 처리시간 0.019초

A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control

  • Cha, Soo-Ho;Jeong, Chun-Seok;Yoo, Chang-Sik
    • ETRI Journal
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    • 제29권4호
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    • pp.463-469
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    • 2007
  • A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

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Ku-Band LNB 수신단의 LNA 설계 (A Study on Design of LNA of LNB module for Ku-band)

  • 곽용수;김형석
    • 한국정보통신설비학회:학술대회논문집
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    • 한국정보통신설비학회 2005년도 하계학술대회
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    • pp.443-447
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    • 2005
  • In this paper, a low noise amplifier(LNA) in a receiver of a Low Noise Block Down Converter (LNB) for direct broadcasting service(DBS) is implemented using GaAs HEMT. The 2-stage LNA is designed for the bandwidth of 11.7GHz - 12.2GHz. The result of a simulation of the LNA using Advanced Design System(ADS) shows that the noise figure is less than 1.4dB, the gain is greater than 23dB and the flatness is 1dB in the bandwidth of 11.7 to 12.2GHz.

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강압형 병렬 컨버터의 제어기 설계 및 검증 (Design and Measurement of Controller for Paralleling Step-down Converter)

  • 박성우;윤희광;박희성;장진백;이상곤
    • 한국조명전기설비학회:학술대회논문집
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    • 한국조명전기설비학회 2009년도 춘계학술대회 논문집
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    • pp.449-452
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    • 2009
  • Optimized controller design for converters are very important because control-loop characteristics of converters determine the dynamic performances of converters. In addition, verification process of the control-loop characteristics by simulation and measurement with real hardware is sure to be performed after all parameters for controller and main power-stage are fixed. In this paper, general process for designing outer-loop controller of paralleling step-down converter is described. Simulation results are also contained for verifying validity of controller design results. Finally, voltage control-loop measurement method is explained and results are compared with simulation outputs.

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Single Pulse-Width-Modulation Strategy for Dual-Active Bridge Converters

  • Byen, Byeng-Joo;Jeong, Byong-Hwan;Choe, Gyu-Ha
    • Journal of Power Electronics
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    • 제18권1호
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    • pp.137-146
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    • 2018
  • This paper describes a single pulse-width modulation control strategy using the Single Pulse-Width Modulation (SPWM) method with a soft-switching technique for a wide range of output voltages from a bidirectional Dual-Active Bridge (DAB) converter. This method selects two typical inductor current waveforms for soft-switching, and proposes a rule that makes it possible to achieve soft-switching without any compensation algorithm from the waveforms. In addition, both the step-up and step-down conditions are analyzed. This paper verifies that the leakage inductance is independent from the rule, which makes it easier to apply in DAB converters. An integrated algorithm, which includes step-up and step-down techniques, is proposed. The results of experiments conducted on a 50-kW prototype are presented. The system efficiency is experimentally verified to be from 85.6% to 97.5% over the entire range.

New Isolated Single-Phase AC-DC Converter for Universal Input Voltage

  • Lee, Ming-Rong;Yang, Lung-Sheng;Lin, Chia-Ching
    • Journal of Power Electronics
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    • 제13권4호
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    • pp.592-599
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    • 2013
  • This paper investigates a new isolated single-phase AC-DC converter, which integrates a modified AC-DC buck-boost converter with a DC-DC forward converter. The front semi-stage is operated in discontinuous conduction mode (DCM) to achieve an almost unity power factor and a low total harmonic distortion of the input current. The rear semi-stage is used for step-down voltage conversion and electrical isolation. The front semi-stage uses a coupled inductor with the same winding-turn in the primary and secondary sides, which is charged in series during the switch-on period and is discharged in parallel during the switch-off period. The discharging time can be shortened. In other words, the duty ratio can be extended. This semi-stage can be operated in a larger duty-ratio range than the conventional AC-DC buck-boost converter for DCM operation. Therefore, the proposed converter is suitable for universal input voltage (90~264 $V_{rms}$) and a wide output-power range. Moreover, the voltage stress on the DC-link capacitor is low. Finally, a prototype circuit is implemented to verify the performance of the proposed converter.

스마트기기용 강압형 DC-DC 변환기 특성해석 (Analysis of a Buck DC-DC Converter for Smart Electronic Applications)

  • 강보경;나재훈;송한정
    • 한국산업융합학회 논문집
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    • 제22권3호
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    • pp.373-379
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    • 2019
  • Nowadays, the IoT portable electronic devices have become more useful and diverse, so they require various supply voltage levels to operate. This paper presents a DC-DC buck converter with pulse width modulation (PWM) for portable electronic devices. The proposed step-down DC-DC converter consists of passive elements such as capacitors, inductors, and resistors and an integrated chip (IC) for signal control to reduce power consumption and improves ripple voltage with the resolution. The proposed DC-DC converter is simulated and analyzed in PSPICE circuit design platform, and implemented on the prototype PCB board with a Texas Instruments LM5165 IC. The proposed buck converter is showed 92.6% of peak efficiency including a load current range of 4-10 mA, 3.29 mV of the voltage ripple at 5 V output voltage for the supply voltage 12 V. Measured and Simulated power efficiency are made good agreement with each other.

고효율 5A용 동기식 DC-DC Buck 컨버터 (High Efficiency 5A Synchronous DC-DC Buck Converter)

  • 황인환;이인수;김광태
    • 한국멀티미디어학회논문지
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    • 제19권2호
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    • pp.352-359
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    • 2016
  • This paper presents high efficiency 5A synchronous DC-DC buck converter. The proposed DC-DC buck converter works from 4.5V to 18V input voltage range, and provides up to 5A of continuous output current and output voltage adjustable down to 0.8V. This chip is packaged MCP(multi-chip package) with control chip, top side P-CH switch, and bottom side N-CH switch. This chip is designed in a 25V high voltage CMOS 0.35um technology. It has a maximum power efficiency of up to 94% and internal 3msec soft start and fixed 500KHz PWM(Pulse Width Modulation) operations. It also includes cycle by cycle current limit function, short and thermal shutdown protection circuit at 150℃. This chip size is 2190um*1130um includes scribe lane 10um.

풍력터빈시뮬레이터와 매트릭스 컨버터를 적용한 PMSG 풍력발전 시스템 모델 개발 (Development of PMSG Wind Power System Model using Wind Turbine Simulator and Matrix Converter)

  • 윤동진;한병문;차한주;이옥용;최남섭
    • 전기학회논문지
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    • 제58권6호
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    • pp.1130-1137
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    • 2009
  • This paper describes a scaled model development of PMSG wind power system using wind turbine simulator and matrix converter. The wind turbine simulator, which consists of an induction motor with vector drive, calculates the output torque of a specific wind turbine using simulation software and sends the torque signal to the vector drive after scaling down the calculated value. The operational feasibility of interconnected PMSG system with matrix converter was verified by computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was conformed by experimental works with a laboratory scaled-model of wind power system. The simulation and experimental results confirm that matrix converter can be effectively applied for the PMSG wind power system.

메시지 의미관계를 이용한 프로토콜 변환 방법에 관한 연구 (A Study on the Protocol Conversion Method using Semantic Relation between Messages)

  • 권운철;심영섭;이동호
    • 한국통신학회논문지
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    • 제19권6호
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    • pp.1107-1114
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    • 1994
  • 본 논문은 적합성을 만족하는 프로토콜 변환 방법에 메시지간의 의미관계를 추가하여 프로토콜 변환기를 생성하는 방법을 제시한다.. 특히, 제안된 방법은 정형화된 기법과 하향식 방법을 도입하여 서로 다른 포로토콜로 구현된 컴퓨터 네트워크 사이의 프로토콜 불일치를 해결하는 효율적인 최다(maximal) 변환기를 유도한다. 따라서 제시된 방법을 사용하여 변환기를 유도할 경우, 불필요한 상태나 전이들의 상당 부분이 쉽게 제거된다.

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Three-Level SEPIC with Improved Efficiency and Balanced Capacitor Voltages

  • Choi, Woo-Young;Lee, Seung-Jae
    • Journal of Power Electronics
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    • 제16권2호
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    • pp.447-454
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    • 2016
  • A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.