• 전기학회논문지
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• 제66권2호
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• pp.459-467
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• 2017

An urban railway power substation consists of three thyristor dual converters. Two converters are connected to up and down trolley line to supply the electric energy or feed the regenerative energy back to the distribution. When the two converters break down, the remaining converter is used in an emergency. One thyristor dual converter system (TDCS) manages the energy of two or three railway stations. If the TDCS fails, the trains stop operating. To solve the problem, this paper proposes the three parallel operation control algorithm of thyristor dual converter system using the emergency converter. The broken TDCS can be replaced by the emergency converter in other TDCS. The effectiveness of this proposed control is verified by simulation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.15-16
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• 2012

This paper is study on a novel high efficiency step up-down converter using loss-less snubber capacitor. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.358-361
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• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 추계학술대회 논문집
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• pp.263-266
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• 2003

The high power factor converters are classified step-up, step-up-down and step-down converter, The power conversion system must be increased switching frequency in order to achieve a small size, a light weight and a low noise. And the power system brings on a high efficiency and high power factor. When a switch of the step down converter is operated with a commercial frequency(60Hz), a reactor using the converter is gone with a great number of harmonics waveforms of low grade. As results of this, the converter is decreased input power factor and is increased system size. To improved these, this paper proposes a PSM(Pulse Size Modulation) control strategy operated with high power factor.

• 전기전자학회논문지
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• 제16권4호
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• pp.335-342
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• 2012

본 논문에서는 고효율과 고역률을 위한 새로운 DCM-ZVS 스텝 업-다운 AC-DC 컨버터에 대해 연구된다. 제안한 DCM-ZVS 컨버터에 사용된 스위칭 소자들은 새로운 유사공진 회로에 의해 소프트 스위칭 기법으로 동작되고, 펄스폭변조(PWM) 방식에 의한 전류불연속모드(DCM)로 구동된다. 제안한 컨버터의 유사공진 회로는 스텝 업-다운 인덕터와 무손실 스너버 커패시터로 구성되고, 또한 DCM에 의해 제어회로 기법과 제어회로 구성이 간단한 장점이 주어진다. 입력 교류 전류파형은 일정 스위칭 주파수에 의한 교류 입력전압의 크기에 비례한 유사 정현파형으로 된다. 그 결과, 제안한 DCM-ZVS 컨버터는 낮은 스위칭 손실과 고효율을 얻을 수 있으며, 컨버터의 입력역률은 거의 단위역률로 된다. 해석적 결과의 타당성은 다양한 컴퓨터 시뮬레이션과 실험 결과를 통해 입증된다.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.149-155
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• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.347-348
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• 2017

This paper presents a new current balancing operation for LED using double-step-down dc-dc converter. The two output currents of the proposed converter can be balanced by charge balance condition although the two output resistances are different. In addition, voltage stresses of the switches of the proposed converter are lower than those of interleaved buck converter. To verify the operation of the proposed converter, simulation program is used.

• Journal of Power Electronics
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• 제19권4호
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• pp.846-857
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• 2019

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.

• 대한전자공학회논문지SP
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• 제39권1호
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• pp.87-96
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• 2002

본 논문에서는 소프트웨어 라디오 수신기의 programmable down converter(PDC) 구현을 위한 효율적인 데시메이션 필터 구조를 제안한다. 제안된 데시메이션 필터는 개선된 cascaded integrator-comb(CIC)필터, cascaded comb, modified halfband 필터 및 halfband 필터, 프로그램 가능한 FIR 필터로 이루어져 있다. 새롭게 제안된 구조는 보상필터를 사용하여 CIC 필터의 통과대역 주파수 감쇠를 보완하고 aliasing억제 능력을 높여, CIC 필터에서 더욱 많은 데시메이션을 담당하도록 설계되었다. 또한 CIC의 보상필터로 인해 cascaded comb 및 modified halfband 필터를 사용 가능토록 하였다. 이러한 구조는 곱셈기가 필요 없기 때문에 연산량을 줄일 수 있고, FIR 필터의 계수를 줄일 수 있다. 실제 구현에서는 기존의 해리스사의 하드웨어에 비해, 곱셈 연산시 연산자 개수는 약 20%, 연산량은 약 50%의 복잡도를 줄일 수 있었다.

• 한국전자통신학회논문지
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• 제12권2호
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• pp.267-272
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• 2017

본 논문에서는 20GHz 이상의 Ka-대역 위성링크에서 대기 중의 감쇠가 심하므로 높은 품질의 영상신호를 수신하기 위하여 최저 잡음지수를 나타내는 하향변환기의 RF-전단부를 제시하였다. 또한 RF-전단부의 CDR, SFDR 및 OIP3을 버짓 분석에 의하여 높은 동적영역을 나타내는 파라미터 값과 선형성을 분석하였다. 설계된 Ka-대역 하향변환기의 전체이득은 61.8dB, 잡음지수는 1.05dB로 매우 우수한 특성 나타내었으며, 설계 제작된 하향변환기는 우수한 선형성을 요구하는 UHD 급의 고화질 영상전송용 Ka-대역 위성방송 하향변환기에 적용할 수 있다.