• Title/Summary/Keyword: Double-layer

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Field Application of the Concrete with the Combination of Drying Shrinkage-Reducing Superplasticizer and Double Layer Bubble Sheet (건조수축 저감형 유동화제 및 2 중 버블시트를 사용한 콘크리트의 현장적용)

  • Han, Cheon-Goo;Oh, Chi-Hyun;Shin, Jae-Kyung
    • Journal of the Korea Institute of Building Construction
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    • v.7 no.1 s.23
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    • pp.107-113
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    • 2007
  • This study investigates the filed application in Daebul Free Trade Zone applying both a flowing method using drying shrinkage-reducing superplasticizer(SRS) and an insulating curing method using double layer bubble sheet. Test results showed that fresh concrete satisfied target slump and air content. A structure adding SRS significantly decreased the total bleeding capacity and accelerated the setting time. As for the crack occurrence, the structure applying the flowing method and double bubble sheets simultaneously exhibited the most favorable crack endurance, while conventional concrete showed more than 1mm size of crack in overall. In addition, a structure applying the flowing concrete method partially presented the micro crack. For the area proportion of crack occurrence, the structure using the double bubble sheets indicated 9.8%, while others applying flowing concrete method was 28%, compared with that of conventional one. For the compressive strength of specimens, standard curing specimens indicated $3{\sim}33%$ higher value than that of specimens cured besides the field construction. The specimens containing SRS improved the strength of $2{\sim}6MPa$, which is $10{\sim}22%$ higher than that of conventional concrete.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

  • Kim, Eun-Kyeom;Kim, Kyong-Min;Son, Dae-Ho;Kim, Jeong-Ho;Lee, Kyung-Su;Won, Sung-Hwan;Sok, Jung-Hyun;Hong, Wan-Shick;Park, Kyoung-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.27-31
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    • 2008
  • We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

A Study on TM Scattering by a Conductive Strip Grating Between a Double Dielectric Layer (2중 유전체층 사이의 완전도체띠 격자구조에 의한 TM 산란에 관한 연구)

  • Yoon, Uei-Joong
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.2
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    • pp.73-79
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    • 2018
  • In this paper, TM(transverse magnetic) scattering problems by a conductive strip grating between a double dielectric layer are analyzed by applying the PMM(point matching method) known as a numerical method of electromagnetic fileld. The boundary conditions are applied to obtain the unknown field coefficients, the scattered electromagnetic fields are expanded in a series of Floquet mode functions, and the conductive boundary condition is applied to analysis of the conductive strip. The most normalized reflected powers of the sharp variations in minimum values are scattered in direction of the other angles except incident angle. Generally, in the case of numerical analysis except for reflection and transmission power in free space, as the dielectric constants of the double dielectric layer increases, the reflected power increases and the transmitted power decreases relatively, respectively. The numerical results for the presented structure of this paper having a grounded double dielectric layer are shown in good agreement compared to those of the existing papers.

Tunnel Magnetoresistance with Plasma Oxidation Time in Double Oxidized Barrier Process (2단계 AlOx 절연층 공정에서 하부절연층의 산화시간에 따른 터널자기저항 특성연구)

  • Lee, Young-Min;Song, Oh-Sung
    • Korean Journal of Materials Research
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    • v.12 no.3
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    • pp.200-204
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    • 2002
  • We fabricated TMR devices which have double oxidized tunnel barrier using plasma oxidation method to form homogeneously oxidized AlO tunnel barrier. We sputtered 10 $\AA$-bottom Al layer and oxidized it by varying oxidation time for 5, 10, 20 sec. Subsequent sputtering of 13 $\AA$ - Al was performed and the matallic layer was oxidized for 120 sec. The electrical resistance changed from 700$\Omega$ to 2700$\Omega$ with increase of oxidation time, while variation of MR ratio was little spreading 27~31% which is larger than that of TMR device of ordinary single tunnel barrier. We calculated effective barrier height and width by measuring I-V curves, from which we found the barrier height was 1.3~1.5 eV, sufficient for tunnel barrier, and the barrier width(<16.2 $\AA$) was smaller than that of directly measured value by the tunneling electron microscopy. Our results may be caused by insufficient oxidation of Al precursor into $Al_2O_3$. However, double oxidized tunnel barriers were superior to conventional single tunnel barrier in uniformity and density. We found that the external magnetic field to switch spin direction of ferromagnetic layer of pinned layer breaking ferro-antiferro exchange coupling was increased as bottom layer oxidation time increased. Our results imply that we were able to improve MR ratio and tune switching field by employing double oxidized tunnel barrier process.

A Study on TM Scattering by a Resistive Strip Grating Between a Double Dielectric Layer (2중 유전체층 사이의 저항띠 격자구조에 의한 TM 산란에 관한 연구)

  • Yoon, Uei-Joong
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.1
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    • pp.49-54
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    • 2021
  • In this paper, n this paper, E-polarized electromagnetic scattering problems by a resistive strip grating between a double dielectric layer are analyzed by applying the PMM(Point Matching Method) known as a numerical method of electromagnetic fileld. The boundary conditions are applied to obtain the unknown field coefficients, and the resistive boundary condition is applied to analysis of the resistive strip. The numerical results for the normalized reflected and transmitted power are analyzed by according as the relative permittivity and thickness of the double dielectric layers, and the resistivity of resistive strip. Overall, when the resistivity of the resistive strip decreased or the relative permittivity of the dielectric layer increased, the reflected power increased, and as the reflected power increased, the transmitted power decreased relatively. Especially, as the relative permittivity of double dielectric layer increases, the minimum value of the variation curve of the reflected power shifted in the direction that the grating period decreased. The numerical results for the presented structure of this paper are shown in good agreement compared to those of the existing papers.

Electrical Quadruple Layer under the AC Electric Field

  • Suh, Yong-Kweon
    • 한국전산유체공학회:학술대회논문집
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    • 2006.10a
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    • pp.167-176
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    • 2006
  • In this paper we show that solutions of the nonlinear Nernst-Planck equation possesses the quadruple-layer structure near the interface when the electrolyte receives a high frequency forcing such as a high-frequency alternating current. Very near to the interface wall, the well-known, classical Stern layer exists. Near to the Stern layer we have the secondly thin layer (to be called inner layer in this paper) where the ion concentrations behave under the same frequency as the external forcing. However, in this layer, the positive and negative ion concentrations develop with the time phase 180-degree different from each other. Next to this second layer, we have the third layer (called middle layer) in which two ion concentrations change with the time period double the forcing, and both concentrations behave in the same time phase. In the outermost layer, i.e. the forth layer, (called outer layer) the ion concentrations show the same-phase development as the third one but decaying very slowly in time. Our assertion is mostly based on the 1-D numerical simulation for the Nernst-Planck equation under a high frequency AC field assuming that the quadruple layer is very thin compared with the length scale representative of the bulk region.

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Ionic Size Effect on the Double Layer Properties: A Modified Poisson-Boltzmann Theory

  • Lou, Ping;Lee, Jin-Yong
    • Bulletin of the Korean Chemical Society
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    • v.31 no.9
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    • pp.2553-2556
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    • 2010
  • On the basis of a simple modified Poisson-Boltzmann (SMPB) theory, taking into account the finite ionic size, the analytic expression for the effect of ionic size on the diffuse layer potential drop at negative charge densities has been given for the simple 1:1 electrolyte. It is shown that the potential drop across the diffuse layer depends on the size of the ions in the electrolyte. For a given electrolyte concentration and electrode charge density, the diffuse layer potential drop in a small ion system is smaller than that in a large ion system. It is also displayed that the diffuse layer potential drop is always less than the value of the Gouy-Chapman (GC) theory, and the deviation increases as the electrode charge density increases for a given electrolyte concentration. These theoretical results are consistent with the results of the Monte-Carlo simulation [Fawcett and Smagala, Electrochimica Acta 53, 5136 (2008)], which indicates the importance of including steric effects in modeling diffuse layer properties.

Dielectric Properties and a Equivalent Circuit of ZnO-Based Varistor (ZnO 바리스터의 유전특성과 등기회로)

  • Rho, Il-Soo;Kang, Dae-Ha
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.12
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    • pp.2166-2172
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    • 2007
  • In this study a low-signal equivalent circuit based on the Double Schottky Barrier model is proposed for ZnO-based varistor. Since pin-lead inductance and stray capacitance are considered in pin-lead type ZnO varistor these inductance and capacitance could be removed from the experimental dielectric data of the varistor. According to the equivalent circuit simulation results the higher the varistor-voltage of varistor sample the capacitance of dielectric layer is larger, and the capacitances of semiconducting layer and depletion layer are smaller, while the parallel resistances of semiconducting layer and depletion layer are more larger values. Spectra of the dielectric loss factor $tan{\delta}$ show 2 peaks in low frequency and high frequency regions respectively. The low-frequency peak is due to the relaxation by deep donors and the high-frequency peak is due to the relaxation by shallow donors. Above results are well consistent with the theoretical mechanism of ZnO varistor.

Experiment and simulation analysis on full scale double-layer concrete shell

  • Thanh Quang Khai Lam;Thi My Dung Do
    • Computers and Concrete
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    • v.31 no.1
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    • pp.9-21
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    • 2023
  • The published studies usually used analytical method, numerical methods or experimental method to determine the stress-strain state and displacement of the single-layer or multi-layer curved shell types, but with a small scale model. However, a full scale multi-layer doubly curved concrete shell roof model should be researched. This paper presents the results of the experiment and simulation analysis involving stress-strain state, sliding between layers, the formation and development of the full scale double-layer doubly curved concrete shell roof when this shell begins to crack. The results of the this study have constructed the load-sliding strain relationship; strain diagram; stress diagram in the shell layers; the Nx, Ny membrane force diagram and deflection of shell. Thisresults by experimental method on a full scale model of concrete have clarified the working of multi-layer doubly curved concrete shell roof. The experimental and simulation results are compared with each other and compared with the Sap2000 software.

Electrical and Optical Properties of ITO Thin Films with Various Thicknesses of SiO2 Buffer Layer for Capacitive Touch Screen Panel (정전용량식 터치스크린 패널을 위한 SiO2 버퍼층 두께에 따른 ITO 박막의 전기적 및 광학적 특성)

  • Yeun-Gun, Chung;Yang-Hee, Joung;Seong-Jun, Kang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.17 no.6
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    • pp.1069-1074
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    • 2022
  • In this study, we prepared ITO thin films on the Nb2O5/SiO2 double buffer layer and investigated electrical and optical properties according to the change of SiO2 buffer layer thickness (40~50nm). The ITO thin film fabricated on the Nb2O5/SiO2 double buffer layer exhibited a broad surface roughness with a small value ranging of 0.815 to 1.181nm, and the sheet resistance was 99.3 to 134.0Ω/sq. It seems that there is no problem in applying the ITO thin film to a capacitive touch screen panel. In particular, the average transmittance in the short-wavelength (400~500nm) region and the chromaticity (b*) of the ITO thin film deposited on the Nb2O5(10nm)/SiO2(40nm) double buffer layer showed significantly improved results as 83.58% and 0.05, respectively, compared to 74.46% and 4.28 of ITO thin film without double buffer layer. As a result, it was confirmed that optical properties such as transmittance in the short-wavelength region and chromaticity were remarkably improved due to the index matching effect in the ITO thin film with the Nb2O5/SiO2 double buffer layer.