• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2072-2074
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• 2001

In this paper, a transmitter and a receiver using two identical Hyper-Chaos that n-double scroll circuits are proposed and a hyper-chaos synchronizations and secure communication are investigated. we are proposed unidirectional coupling of identical n-double scroll cell for hyper-chaos synchronization. We've shown that simulation result is synchronization and secure communication.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.2 s.3
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• pp.97-101
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• 2003

A MMIC (monolithic microwave integrated circuit) mixer chip using the Schottky diode of an InGahs/CaAs p-HEMT process has been developed for the receiver down converter of Ku-band. A different approach to the MMIC mixer structure is applied for reducing the chip size by the exchange of ports between If and LO. This MMIC covers with RF (14.0 - 14.5 GHz) and If (12.252 - 12.752 GHz). According to the on-wafer measurement, the miniature (3.3X3.0 m) MMIC mixer demonstrates conversion loss below 9.8 dB, RF-to-IF isolation above 23 dB, LO-to-IF isolation above 38 dB, respectively.

• Journal of IKEEE
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• v.25 no.2
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• pp.280-284
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• 2021

In this paper, a new ESD protection circuit is proposed to improve the snapback characteristics. The proposed a new structure ESD protection circuit applying the conventional SCR structural change and stack structure. The electrical characteristics of the structure using penta-well and double trigger were analyzed, and the trigger voltage and holding voltage were improved by applying the stack structure. The electron current and total current flow were analyzed through the TCAD simulation. The characteristics of the latch-up immunity and excellent snapback characteristics were confirmed. The electrical characteristics of the proposed ESD protection circuit were analyzed through HBM modeling after forming a structure through TCAD simulator.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.229-230
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• 2015

This paper presents practical details about control-loop design and dynamic analysis for a voltage-mode controlled isolated double step-down DC-DC converter. Graphical loop gain method is used to design the feedback compensation and analyze the closed-loop performance of isolated double step-down DC-DC converter. The results of the control design and closed-loop analysis are validated by experiments on a prototype converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• International journal of advanced smart convergence
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• v.11 no.4
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• ETRI Journal
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• v.26 no.6
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• pp.560-564
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• 2004

An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.6
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• pp.908-919
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• 1998

This paper describes implementation and simulation of Chua's oscillator circuits with a cubic non-linear resistor. The two-terminal nonlinear resistor NR consists of one Op Amp two multipliers and five resistors. The Chua's oscillator circuit is implemented with analog electronic devices. Period-1 limit cycle period-2 limit cycle period-4 limit cycle and spiral attractor double-scroll attractor and 2-2 window are observed experimentally from the laboratory model and simulated by computer for the presented model. Comparing the result of experiments and simulations the spectrums are satisfied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.