• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Journal of IKEEE
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• v.24 no.1
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• pp.161-169
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• 2020

In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the V_TP(Program Threshold Voltage) and the V_TE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and V_T and erase V_T, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.819-824
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• 2000

In this research, the etching characteristics of Ta thin film with chlorine plsama have been studied by Electron Cyclotron Resonance (ECR) plasma etching system. The effects of microwave power, RF bias power, working pressure and gas chemistry on the etching profiles have been investigated. The microloading effect, which was observed at fine pattern formation, was effectively suppressed by double step etching, and anisotropic $0.2{\mu\textrm{m}}$ L&S patterns were successfully generated.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.395-398
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA(240$^{\ast}$320) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.981-982
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• 1998

We fabricated sampled fiber grating by double-exposure method. First, a short-period grating was written into the hydrogen-loaded single mode fiber and then the refractive index was modulated over it by an amplitude mask. It was observed that several transmission dips appear due to the index modulation. The thermal and strain responses were measured over $40-180^{\circ}C$ and $0-1800\mu\varepsilon,$ respectively. The dips have the same and linear sensitivity to both physical quantities over the range of measurement.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.147-150
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• 2007

This paper presents an advanced RFID reader system implementing multi-protocols and multi-standards at 900MHz. In accordance with the strict regulations specified by ISO 18000-6 B-Type and EPC Global Gen 2, we have designed corresponding systemic factors which meet the domestic radio frequency utilizing bands of 910-914MHz. In addition, we develop numerous crucial factors of system compatibility options including SSB (Single-Side Band) and DSB (Double-Side Band) specifications, also OOK (On-Off Keying), ASK (Amplitude Shift Keying) and PR-ASK (Phase Reversed-Amplitude Shift Keying) modulation formula. Remarkable technical features of system in this paper can be the direct conversion routines using I/Q Modulation/Demodulation respectively, and Full-Duplex formulation operating at identical frequency bands.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• ETRI Journal
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• v.25 no.4
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• pp.270-273
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• 2003

This paper presents a simple process to integrate thin-film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3${\mu}m$ were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin-film inductor showed an inductance of 0.49${\mu}H$ and a Q factor of 4.8 at 8 MHz. The DC-DC converter with the monolithically integrated thin-film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC-DC converter with the monolithic thin-film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.929-936
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• 1990

This paper describes the method of the Korean character recognition by means of feature points extraction. Also, the preprocessing neural chip for noise elimination, smoothing, thinning and feature point extraction has been designs. The subpatterns were separated by means of advanced index algorithm using mask, and recognized by means of feature points classification. The separation of the Korean character subpatterns was abtained about 97%, and the recognition of the Korean characters was abtained about 95%. The preprocessing neural chip was simulated on SPICE and layouted by double CMOS 2\ulcorner design rule.