• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.486-488
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• 1996

A dc-dc converter which transfers l2-48W of power(regulated output voltage 24V) across a large, variable air gap(1-2cm) has been designed. This converter employs double resonance to compensate the large leakage inductance of the primary and secondary of the transcutaneous transformer. To maximize the effect of resonance, a constant frequency, duty cycle control method is used. The duty cycle control presents advantages over a frequency control in terms of increase in dc voltage gain and reduction of the primary current. The analysis and design procedure for the proposed scheme is presented and the performance result is simulated and verified experimentally.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.176-181
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• 2015

In the DC electric railway system, the effective use of regenerative break energy is an important issue. Since regenerative break energy causes voltage rise or drop in the system, it should be also solved effectively. To solve the problems, applying electric double layer capacitor (EDLC) or voltage source converter (VSC) to the DC electric railway system has been studying. In this paper, the coordination of EDLC and VSC is proposed to solve the problem effectively with its coordinated control algorithm. The proposed method is tested to show its feasibility using Matlab/Simulink.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.83-84
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• 2014

This paper proposes the development of double conversion Uninterruptible Power Supply using 3-Level Converter/TNPC Inverter. The Rectifier of proposed system is operating not only 3-Level boost PFC but also battery discharger. The Inverter is converting DC voltage to AC voltage. And in terms of the efficiency, 3-Level TNPC inverter is improved compared to the origin 2-Level type. To verify the validity of proposed system, experiments were carried out.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.276-277
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• 2010

This paper describes the control of a utility-connected doublefed induction machine (DFIM) for wind power generation systems (WPGS). Real and reactive powers (PQ) at the stator side of DFIM are strictly controlled to supply the power to the grid without any problems. In this paper the control is realized using Fuzzy PI controller based on the stator-flux orientation control.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.11
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• pp.37-46
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• 2013

This paper proposes the boost type bidirectional zero current switching(ZCS) DC/DC converter of transformer series construction for electric vehicle operation using low voltage battery. This converter can high boost through the double voltage circuit and series construction of output part using two converters. This converter system has the advantages that bidirectional power transfer is excellent, size and making of transformer because of this converter keeps the transformation ratio to 1:1. Proposed DC/DC converter uses the ZCS method to decrease the switching loss. By replacing reactance ingredients of L-C resonance circuit for ZCS with leakage inductance ingredients of high frequency transformer and half-bridge capacitor it reduces system size and expense because of not add special reactor. It can confirm to output of high voltage to operate the electric vehicle with low voltage of input and operation of ZCS in all load region through the result of PSIM simulation and experiment.

• Journal of Power Electronics
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• v.12 no.3
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.882-885
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• 2003

In this paper, nonlinear echo cancellation using a correlation LMS (CLMS) algorithm is proposed to cancel the undesired nonlinear echo signals generated in the hybrid system of the telephone network. In the telephone network, the echo signals may result the degradation of the network performance. Furthermore, digital to analog converter (DAC) and analog to digital converter (ADC) may be the source of the nonlinear distortion in the hybrid system. The adaptive filtering technique based on the nonlinear Volterra filter has been the general technique to cancel such a nonlinear echo signals in the telephone network. But in the presence of the double-talk situation, the error signal for tap adaptations will be greatly larger, and the near-end signal can cause any fluctuation of tap coefficients, and they may diverge greatly. To solve a such problem, the correlation LMS (CLMS) algorithm can be applied as the nonlinear adaptive echo cancellation algorithm. The CLMS algorithm utilizes the fact that the far-end signal is not correlated with a near-end signal. Accordingly, the residual error for the tap adaptation is relatively small, when compared to that of the conventional normalized LMS algorithm. To demonstrate the performance of the proposed algorithm, the DAC of hybrid system of the telephone network is considered. The simulation results show that the proposed algorithm can cancel the nonlinear echo signals effectively and show robustness under the double-talk situations.