• Title/Summary/Keyword: Double converter

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A Novel Integrated Generator Converter System for HVDC and Eddy Current of it's Solid Rotor Core (HVDC 송전을 위한 새로운 집적변환 발전기 계통과 그 회전자 중심의 와전류)

  • 이은웅;김일중;이민명
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.37 no.7
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    • pp.434-441
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    • 1988
  • This paper proposes a new invention of the integrated generator converter system for the HVDC transmission. And it analyses the general formula for eddy currents in the rotor iron using the double Fourier series in order to trace the smallest eddy current losses of the system which connects a new designed synchronous generator windings or conventional synchronous generator windings with the v Graetz bridges.

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Implementation of Fuzzy Controller for Rotor Side Converter of DFIG

  • Sastrowijoyo, Fajar;Choi, Jaeho
    • Proceedings of the KIPE Conference
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    • 2012.11a
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    • pp.131-132
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    • 2012
  • Implementation of fuzzy controller for the rotor side converter of a utility-connected double-fed induction generator (DFIG) for wind power generation systems (WPGS) described in this paper. In the control schemes, real and reactive powers (PQ) at the stator side of DFIG are strictly controlled to supply the power to the grid. A TMS320VC33 DSP is selected as the controller of this system.

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Design of a 12 bit current-mode folding/interpolation CMOS A/D converter (12비트 전류구동 폴딩.인터폴레이션 CMOS A/D 변환기 설계)

  • 김형훈;윤광섭
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.986-989
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    • 1999
  • An 12bit current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current - mode multiplied folding amplifier is employed not only to reduced the number of reference current source, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The simulation result shows the power dissipation of 280㎽ with a power supply of 5V.

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Bidirectional Charging/Discharging Digital Control System for Eco-friendly Capacitor Energy Storage Device Implemented by TMS320F28335 chip (TMS320F28335로 구현한 친환경 커패시터 전력저장장치의 양방향 디지털 제어 충/방전 시스템)

  • Lee, Jung-Im;Lee, Jong-Hyun;Jung, An-Yoel;Lee, Choon-Ho;Park, Joung-Hu;Jeon, Hee-Jong
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.3
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    • pp.188-198
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    • 2010
  • Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

Double Rail-to-Rail NTV SAR ADC (두 배의 Rail-to-Rail 입력 범위를 갖는 NTV SAR ADC)

  • Jo, Yong-Jun;Seong, Kiho;Seo, In-Shik;Baek, Kwang-Hyun
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1218-1221
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    • 2018
  • This paper presents a low-power 0.6-V 10-bit 200-kS/s double rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme allows input signal with 4 times power which is compared with conventional one by applying proposed rail-to-rail scheme, and that improves signal-to-noise ratio(SNR) of NTV SAR ADCs. The prototype was designed using 65-nm CMOS technology. At a 0.6-V supply and $2.4-V_{pp}$ (differential) and 200-kS/s, the ADC achieves an SNDR of 59.87 dB and consumes 364.5-nW. The ADC core occupies an active area of only $84{\times}100{\mu}m^2$.

A Study on the Fluid Flow Characteristic in Catalytic Converter for Various Inlet and Outlet Header Shapes (입.출구 형상변화에 따른 촉매변환기 내의 유동특성에 관한 연구)

  • Lee, Eun-Ho;Lee, Chul-Ku;Yoo, Jai-Suk;Lee, Jong-Hwa
    • Transactions of the Korean Society of Automotive Engineers
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    • v.7 no.7
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    • pp.187-194
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    • 1999
  • In the design of catalytic converter, velocity distribution is more important than pressure drop because monolith pressure drop is about 80% of overall pressure drop. For the catalytic converter with single diffuser, pressure drop is decreased as the angle of diffuser decrease, but when the angle is below 18$^{\circ}$, the effect is almost negligible . For the catalytic converter with double diffuser, variation of the angle of the first diffuser shows the same trend as the pressure drop while the shape of diffuser gives little influence on that The outlet shape gives negligible effect on the pressure drop and velocity . distribution . Results show that recirculation region of commercial model is aoubt 30% of the total area in the front of monolith. For the catalytic converter with Model 11 that was presented in the study, recirculation region was not detected more uniform velocity distribution was obtained, and pressure drop was also decreased.

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A CMOS Readout Circuit for Uncooled Micro-Bolometer Arrays (비냉각 적외선 센서 어레이를 위한 CMOS 신호 검출회로)

  • 오태환;조영재;박희원;이승훈
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.1
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    • pp.19-29
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    • 2003
  • This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

Fabrication of the 7$\times$7 mm Planar Inductor for 1W DC-DC Converter (1W DC-DC 컨버터를 위한 7$\times$7 mm 평면 인덕터의 제조)

  • Bae, Seok;Ryu, Sung-Ryong;Kim, Choong-Sik;Nam, Seoung-Eui;Kim, Hyoung-June;Min, Bok-Ki;Song, Jae-Sung
    • Journal of the Korean Magnetics Society
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    • v.11 no.5
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    • pp.222-225
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    • 2001
  • The planar type inductors have a good potential for the application of miniaturized low power DC-DC converters. For those high quality application, the reduction of coil loss and also magnetic films which have good high frequency properties are required. Fabricated inductor was consisted of FeTaN/Ti magnetic film and electroplated Cu coil thickness of 100$\mu\textrm{m}$ and $SiO_2$ as a insulating layer. The inductor was designed double rectangular spiral shape for magnetic field highly confining within the device. The measured value of inductance and resistance were 980 nH and 1.7 $\Omega$ at 1 MHz as operating frequency of device. The Q factor is 3.55 at 1 MHz.

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Output Waveform Improvement of Double-Connected 3-Phase Voltage Source Inverter by Single-Phase Inverter (단상 인버터의 동작에 의한 이중접속 3상 전압원 인버터의 출력파형 개선)

  • 최세완;양승욱
    • The Transactions of the Korean Institute of Power Electronics
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    • v.6 no.1
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    • pp.21-26
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    • 2001
  • This paper proposes a new double-connected 3-phase voltage source inverter with improved output voltage waveform. An auxiliary single-phase inverter injects a ripple voltage into the double-connected inverter to converter 12-step operation to 36-step operation. The KVA rating of the output phase-shifting transformer is reduced by employing a harmonic canceling reactor. The whole rectifier-inverter system including the proposed technique is introduced, and the experimental results are provided.

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A Fully Integrated Thin-Film Inductor and Its Application to a DC-DC Converter

  • Park, Il-Yong;Kim, Sang-Gi;Koo, Jin-Gun;Roh, Tae-Moon;Lee, Dae-Woo;Yang, Yil-Suk;Kim, Jung-Dae
    • ETRI Journal
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    • v.25 no.4
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    • pp.270-273
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    • 2003
  • This paper presents a simple process to integrate thin-film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3${\mu}m$ were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin-film inductor showed an inductance of 0.49${\mu}H$ and a Q factor of 4.8 at 8 MHz. The DC-DC converter with the monolithically integrated thin-film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC-DC converter with the monolithic thin-film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.

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