• 제목/요약/키워드: Disturbance Fault

검색결과 102건 처리시간 0.023초

분산전원의 Fault Ride Through를 고려한 방향성 과전류 계전기 최적 정정법에 관한 연구 (A Study on the Optimal Setting Method of Directional Overcurrent Relay Considering Fault Ride Through of Distributed Generation)

  • 송진솔;조규정;김지수;신재윤;김동현;김철환
    • 전기학회논문지
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    • 제67권8호
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    • pp.1002-1008
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    • 2018
  • Fault Ride Through(FRT) requirement prevents disconnections of distributed generations during the specific time on disturbance condition for system stability. However, since there is a limitation to the FRT capability of distributed generation, and the protection system needs to clear the fault quickly before the distributed generation is disconnected. Therefore, this paper proposes a novel optimal setting method of directional overcurrent relay considering FRT of distributed generation. The proposed method reduces the probability of disconnections of the distributed generation in disturbance without additional equipment considering the FRT capability of the distributed generation by calculating the optimal relay setting through the Genetic Algorithm(GA).

비선형 보일러 시스템에서의 이상허용제어 (Fault Tolerant Control for Nonlinear Boiler System)

  • 윤석민;김대우;이명의;권오규
    • 제어로봇시스템학회논문지
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    • 제6권4호
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    • pp.254-260
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    • 2000
  • This paper deals with the development of fault tolerant control for a nonlinear boiler system with noise and disturbance. The MCMBPC(Multivariable Constrained Model Based Predictive Control) is adopted for the control of the specific boiler turbin model. The fault detection and diagnosis are accomplished with the Kalman filter and two bias estimators. Once a fault is detected, two Bias estimators are driven to estimate the fault and to discriminate Process fault and sensor fault. In this paper, a fault tolerant control scheme combining MCMBPC with a fault compensation method based on the bias estimator is proposed. The proposed scheme has been applied to the nonlinear boiler system and shown a satisfactory performance through some simulations.

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계통 사고 발생시 전압 변동을 최소화 하기위한 계통연계형 PCS의 제어 기법 (Control of Grid Connected Type PCS to Minimize Voltage Disturbance at Line Fault)

  • 정재헌;권창근;노의철;김인동;김흥근;전태원
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2011년도 추계학술대회
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    • pp.257-258
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    • 2011
  • This paper describes a new method for the seamless operation mode transfer of a PCS with minimized voltage disturbance. The proposed method provides reduced STS turn off time after line fault and smooth mode change between current and voltage control of the PCS. The usefulness of the method is verified through simulations with the consideration of the time delay in detecting a line fault and SCR turn-off time.

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A Realization of Reduced-Order Detection Filters

  • Kim, Yong-Min;Park, Jae-Hong
    • International Journal of Control, Automation, and Systems
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    • 제6권1호
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    • pp.142-148
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    • 2008
  • In this paper, we deal with the problem of reducing the order of the detection filter for the linear time-invariant system. Even if the detection filter is generally designed in the form of full order linear observer, we show that it is possible to reduce its order when the response of fault signals is limited to a subspace of the estimation state space. We propose a method to extract the subspace using the observer canonical form considering the dynamics related to the remaining subspace acts as a disturbance. We designed a reduced order detection filter to reject the disturbance as well as to guarantee fault detection and isolation. A simulation result for a 5th order system is presented as an illustrative example of the proposed design method.

임베디드 NAND-형 플래시 메모리를 위한 Built-In Self Repair (Built-In Self Repair for Embedded NAND-Type Flash Memory)

  • 김태환;장훈
    • 정보처리학회논문지:컴퓨터 및 통신 시스템
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    • 제3권5호
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    • pp.129-140
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    • 2014
  • 기존의 메모리에서 발생하는 다양한 고장들을 검출하기 위한 기법으로 BIST(Built-in self test)가 있고 고장이 검출되면 Spare를 할당하여 수리하는 BIRA(Built-in redundancy analysis)가 있다. 그리고 BIST와 BIRA를 통합한 형태인 BISR(Built-in self repair)를 통해 전체 메모리의 수율을 증가시킬 수 있다. 그러나 이전에 제안된 기법들은 RAM을 위해 제안된 기법으로 RAM의 메모리 구조와 특성이 다른 NAND-형 플래시 메모리에 사용하기에는 NAND-형 플래시 메모리의 고유 고장인 Disturbance를 진단하기 어렵다. 따라서 본 논문에서는 NAND-형 플래시 메모리에서 발생하는 Disturbance 고장을 검출하고 고장의 위치도 진단할 있는 BISD(Built-in self diagnosis)와 고장 블록을 수리할 수 있는 BISR을 제안한다.

속도 오차 외란이 반작용 휠 제어에 미치는 영향에 관한 실험적 연구 (Experimental Study on Effects of Speed Error Disturbance on Reaction Wheel Control)

  • 김지철;이형준;유지훈;오화석
    • 항공우주시스템공학회지
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    • 제10권1호
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    • pp.95-102
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    • 2016
  • There are many possible disturbance sources on such a spacecraft, but reaction wheel assembly (RWA) which is generally used for spacecraft attitude control is anticipated to be the largest. These effects on degradation of performance of spacecraft such as attitude stability. In reaction wheel, disturbance caused by imbalance and speed error. It is hard to emulate speed error disturbance because it is not coincide with wheel frequency. This paper concentrates on emulating and analyzing the speed error disturbance. Firstly, classify the causes that lead to speed error disturbance which generate RPM fluctuation. Secondly, simulated with disturbance driver module and reaction wheel assembly which are developed by Spacecraft Control Lab. Experimental investigations have been carried out to test the disturbance emulator module as a disturbance generator for RWA. Measurements and test have been conducted on various fault. Frequency analysis of test data show that speed error disturbance effects on wheel settling wheel speed or fluctuation type.

Fault Diagnosis and Accommodation of Linear Stochastic Systems with Unknown Disturbances

  • Lee, Jong-Hyo;Joon Lyou
    • Transactions on Control, Automation and Systems Engineering
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    • 제4권4호
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    • pp.270-276
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    • 2002
  • An integrated robust fault diagnosis and fault accommodation strategy for a class of linear stochastic systems subjected to unknown disturbances is presented under the assumption that only a single fault may occur at a given time. The strategy is based on the fault isolation and estimation using a bank of robust two-stage Kalman filters and introduction of the additive compensation input for cancelling out the fault's effect on the system. Each filter is set up such that the residual is decoupled from unknown disturbances and fault with the influence vector designed in the filter. Simulation results for the simplified longitudinal flight control system with parameter uncertainties, process and sensor noises demonstrate the effectiveness of the present approach.

Protection Assessment using Reduced Power System Fault Data

  • Littler, T.B.
    • Journal of Electrical Engineering and Technology
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    • 제2권2호
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    • pp.172-177
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    • 2007
  • Wavelet transforms provide basis functions for time-frequency analysis and have properties that are particularly useful for the compression of analogue point on wave transient and disturbance power system signals. This paper evaluates the compression properties of the discrete wavelet transform using actual power system data. The results presented in the paper indicate that reduction ratios up to 10:1 with acceptable distortion are achievable. The paper discusses the application of the reduction method for expedient fault analysis and protection assessment.

FPGA-based ARX-Laguerre PIO fault diagnosis in robot manipulator

  • Piltan, Farzin;Kim, Jong-Myon
    • Advances in robotics research
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    • 제2권1호
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    • pp.99-112
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    • 2018
  • The main contribution of this work is the design of a field programmable gate array (FPGA) based ARX-Laguerre proportional-integral observation (PIO) system for fault detection and identification (FDI) in a multi-input, multi-output (MIMO) nonlinear uncertain dynamical robot manipulators. An ARX-Laguerre method was used in this study to dynamic modeling the robot manipulator in the presence of uncertainty and disturbance. To address the challenges of robustness, fault detection, isolation, and estimation the proposed FPGA-based PI observer was applied to the ARX-Laguerre robot model. The effectiveness and accuracy of FPGA based ARX-Laguerre PIO was tested by first three degrees of the freedom PUMA robot manipulator, yielding 6.3%, 10.73%, and 4.23%, average performance improvement for three types of faults (e.g., actuator fault, sensor faults, and composite fault), respectively.

최소자승법을 이용한 적응형 데이터 윈도우의 거리계전 알고리즘 (Distance Relaying Algorithm Based on An Adaptive Data Window Using Least Square Error Method)

  • 정호성;최상열;신명철
    • 대한전기학회논문지:전력기술부문A
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    • 제51권8호
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    • pp.371-378
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    • 2002
  • This paper presents the rapid and accurate algorithm for fault detection and location estimation in the transmission line. This algorithm uses wavelet transform for fault detection and harmonics elimination and utilizes least square error method for fault impedance estimation. Wavelet transform decomposes fault signals into high frequence component Dl and low frequence component A3. The former is used for fault phase detection and fault types classification and the latter is used for harmonics elimination. After fault detection, an adaptive data window technique using LSE estimates fault impedance. It can find a optimal data window length and estimate fault impedance rapidly, because it changes the length according to the fault disturbance. To prove the performance of the algorithm, the authors test relaying signals obtained from EMTP simulation. Test results show that the proposed algorithm estimates fault location within a half cycle after fault irrelevant to fault types and various fault conditions.