• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$