• 제목/요약/키워드: Distributed Impedance

검색결과 156건 처리시간 0.026초

위상 배열 안테나 임피던스 부정합에 따른 실시간 지연회로의 위상 지연 오차 및 영향 분석 (Analysis of TTD Phase Delay Error and Its Effect on Phased Array Antenna due to Impedance Mismatch)

  • 윤민영;남상욱
    • 한국전자파학회논문지
    • /
    • 제29권11호
    • /
    • pp.828-833
    • /
    • 2018
  • 일반적으로 반사파 및 공진이 위상 왜곡에 영향을 준다고 많이 알려져 있지만, 그 두 가지 이유 이외에 안테나 임피던스 변화에 따라서도 위상 지연을 왜곡시킬 수 있다는 것을 확인하였다. 본 논문에서는 상호 결합 영향을 모두 고려한 안테나 임피던스 $Z_A$에 따른 위상 지연 오차를 분석하고, 이에 따른 빔조향 특성을 확인하였다. 안테나 임피던스에 대한 반사손실의 최대값($RL_{max}$)이 -10 dB와 -7 dB일 때 모든 주파수에서 각각 $0.051{\lambda}$에 해당하는 $18.5^{\circ}$$0.074{\lambda}$에 해당하는 $26.5^{\circ}$의 최대 위상 지연 오차가 발생하는 것을 확인하였다. 8개의 선형 배열 안테나를 통해 몬테 카를로 시뮬레이션을 진행한 결과, $18.5^{\circ}$$26.5^{\circ}$의 균등 분포 위상 오차를 갖는 상황에서 각각 $0{\sim}30^{\circ}$의 빔조향을 했을 때 목표 빔조향각과 해당 위상 오차에 의해 틀어져서 관측되는 조향각 사이의 RMS 오차는 $0.19{\sim}0.4^{\circ}$이고, 표준편차는 $0.14{\sim}0.33^{\circ}$이다. 이때 사이드 로브 레벨은 -12.8 dB의 이론치로부터 위상 오차에 의해 0.74~1.21 dB 만큼 증가하고 사이드 로브 레벨 증가량의 표준 편차는 0.31~0.51 dB를 갖는다. 이를 스파이럴 안테나 8개 배열 구조를 설계하여 검증하였다.

Helical Resonator 배열을 통한 대면적 고밀도 Plasma Source (Preparation of Large Area Plasma Source by Helical Resonator Arrays)

  • 손민영;김진우;박세근;오범환
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
    • /
    • pp.282-285
    • /
    • 2000
  • Four helical resonators are distributed in a 2 ${\times}$ 2 array by modifying upper part of the conventional reactive ion etching(RIE) type LCD etcher in order to prepare a large area plasma source. Since the resonance condition of the RF signal to the helical antenna, one RF power supply is used for delivering the power efficiently to all four helical resonators without an impedance matching network Previous work of 2 ${\times}$ 2array inductively coupled plasma(ICP)requires one matching circuit to each ICP antenna for more efficient power deliverly Distributions of ion density and electron temperature are measured in terms of chamber pressure, gas flow rate and RF power . By adjusting the power distribution among the four helical resonator units, argon plasma density of higher than 10$\^$17/㎥ with the uniformity of better than 7% can be obtained in the 620 ${\times}$ 620$\textrm{mm}^2$ chamber.

  • PDF

공진형 인버터에 있어서 RF Noise 저감을 위한 Snubber 최적 회로 설계에 관한 연구 (Optimal Snubber Design Strategy for the Resonant Inverter to Reduce RF Noise)

  • 김은수;유동욱;오성철;이종무
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1990년도 추계학술대회 논문집 학회본부
    • /
    • pp.380-383
    • /
    • 1990
  • When the MOSPET is applied as a switching device for the resonant inverter, a damped oscillating noise is appeared at specific frequency band. This damped Oscillation is caused by the series and parallel resonance due to distributed circuit parameter of snubber and main circuit. This paper describes the frequency-impedance characteristic of the resonant inverter and optimal snubber design strategy to reduce the RF noise.

  • PDF

장거리 병렬 송전선로용 대지 정전용량 보상에 의한 고장점 표정 알고리즘 (Fault Location Algorithm with Ground Capacitance Compensation for Long Parallel Transmission Line)

  • 박철원;김삼용;신명철
    • 전기학회논문지P
    • /
    • 제54권4호
    • /
    • pp.163-170
    • /
    • 2005
  • This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

송전선로의 고장점 표정 알고리즘 (An Algorithm of fault Location Technique for Long Transmission Line)

  • 박철원;김삼룡;신명철;남시복;이복구
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2002년도 하계학술대회 논문집 A
    • /
    • pp.145-147
    • /
    • 2002
  • In this paper, the improved fault locating method using distributed parameter which calculating the reduced voltage and current according to the ground capacitance in long transmission line was proposed. For the purpose of the fault locating algorithm non influenced source impedance, the loop method was used in the system modeling analysis. To enhance the fault locating, zero sequence of the fault current which is variable according to ground capacitance was not used but positive and negative sequence. System model was simulated using EMTP software. To verify the accuracy of proposed method, in different cases 64 sampled data per cycle was used and 160km and 300km long transmission line has fault resistance $0{\Omega}\;and\;100{\Omega}$ respectively was compared.

  • PDF

Inter-Phase Transformers를 이용한 고온 초전도 케이블의 층간 전류 등분배 방안 (Uniform Current Distribution among Conductor Layers in HTS Cables Using Inter-Phase Transformers)

  • 최용선;황시돌;현옥배;임성우;박인규
    • Progress in Superconductivity
    • /
    • 제5권2호
    • /
    • pp.144-148
    • /
    • 2004
  • Uniform current distribution among conductor layers in HTS cables using IPTs (inter-phase transformers) was investigated. Conventional methods for current distribution, in which resistors are inserted to conductor layers, causes additional loss. In contrast, IPTs, which use magnetic coupling, make it possible that the current in parallel circuits is distributed uniformly with any load, and minimize the loss. In this study, IPTs were designed and fabricated for examination of uniform current distribution in the conductor layers of HTS cables. The ITP was designed through calculation of its impedance that can cancel the inductance of the conduction layers. The experimental setup consisted of four IPTs and four inductors that simulate the conductor layer inductance. Each layer was designed to feed 10 A. We examined the behavior of current distribution with IPTs for various layer inductances.

  • PDF

Islanding Prevention Method for Photovoltaic System by Harmonic Injection Synchronized with Exciting Current Harmonics of Pole Transformer

  • Yoshida, Yoshiaki;Fujiwara, Koji;Ishihara, Yoshiyuki;Suzuki, Hirokazu
    • Journal of international Conference on Electrical Machines and Systems
    • /
    • 제3권3호
    • /
    • pp.331-338
    • /
    • 2014
  • When large penetration of the distributed generators (DGs) such as photovoltaic (PV) systems is growing up in grid system, it is important to quickly prevent islanding caused by power system fault to ensure electrical safety. We propose a novel active method for islanding prevention by harmonic injection synchronized with the exciting current harmonics of the pole transformer to avoid mutual interference between active signals. We confirm the validity of the proposed method by performing the basic tests of islanding by using a current source superimposed the harmonic active signal. Further, we carry out the simulation using PSCAD/EMTDC, and verify the fast islanding detection.

ULTC 와 SVR 이 설치된 배전계통에서 LDC Parameters 을 고려한 최대 DG 용량 산정 (The Installable Maximum DG Capacity Considering LDC Parameters of ULTC and SVR in Distribution Systems)

  • 김미영
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2008년도 제39회 하계학술대회
    • /
    • pp.27-28
    • /
    • 2008
  • For stable and sustainable energy supply, distributed generator (DG) has become an essential and indispensable element from environmental and energy security perspectives. However, installation of DG in distribution systems may cause negative affects on feeders because power outputs of DG could be changed irregularly. One of major negative affects is variation in voltage profile. In general, voltage regulation devices such as under load tap changer (ULTC) at distribution substation and step voltage regulator (SVR) along feeder in distribution system are used to maintain customers' receiving voltage within a predetermined range. These regulators are controlled by line drop compensation (LDC) method which calls for two parameters; the equivalent impedance and the load center voltage. Therefore, consideration of DG outputs in the LDC parameter design procedure may give large impact on the installable DG capacity. This paper proposes a method that estimates maximum Installable DG capacity considering LDC parameters of ULTC and SVR. The proposed algorithm is tested with model network.

  • PDF

전력선 통신 응용을 위한 저압 댁내망의 채널 특성 분석 기법에 관한 연구 (A Study on the channel characteristics of the household AC power line used for the low bit rate communication home network)

  • 안남호;장태규;황경태
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2001년도 하계학술대회 논문집 A
    • /
    • pp.305-307
    • /
    • 2001
  • In this paper, the household AC power line network is characterized for the low bit rate power line communication (PLC) in the frequency range from 10kHz to 450kHz. Various types of electric apparatus and the power lines constitute the network topology, and the PLC channel transfer function and the channel impedance are derived based on the constructed network topology. The channel characteristics derived with the lumped circuit model and the distributed circuit model are compared using the computer simulations. The effect of the wave reflection and signal distortions are also investigated.

  • PDF

80-MW 클라이스트론 부하용 200-MW 펄스 트랜스포머의 성능시험 (Performance Test of 200-MW Pulse Transformer for 80-MW Klystron Load)

  • 장성덕;오종석;손윤규;조무현
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1999년도 하계학술대회 논문집 E
    • /
    • pp.2167-2169
    • /
    • 1999
  • A pulse transformer producing pulses with the peak power of 200-MW (400 kV 500 A at load side with $4.4{\mu}s$ flat-top) is required to drive the 80-MW pulsed klystron in the PLS linac. We have designed and manufactured the high power pulse transformer with 1 : 17 turn ratio. Its primary functions are to match the impedance of klystron tube to the modulators, and to provide step-up of the voltage. To obtain a fast rise time of the pulse voltage. Low leakage inductance and low distributed capacitance design is very important. In this paper, we discuss the equivalent circuit analysis of the pulse transformer, and present the full power performance test results of pulse transformer.

  • PDF