• 제목/요약/키워드: Dissipation blocks

검색결과 40건 처리시간 0.025초

Research on hysteretic characteristics of EBIMFCW under different axial compression ratios

  • Li, Sheng-cai;Lin, Qiang
    • Earthquakes and Structures
    • /
    • 제22권5호
    • /
    • pp.461-473
    • /
    • 2022
  • Energy-saving block and invisible multiribbed frame composite wall (EBIMFCW) is an important shear wall, which is composed of energy-saving blocks, steel bars and concrete. This paper conducted seismic performance tests on six 1/2-scale EBIMFCW specimens, analyzed their failure process under horizontal reciprocating load, and studied the effect of axial compression ratio on the wall's hysteresis curve and skeleton curve, ductility, energy dissipation capacity, stiffness degradation, bearing capacity degradation. A formula for calculating the peak bearing capacity of such walls was proposed. Results showed that the EBIMFCW had experienced a long time deformation from cracking to failure and exhibited signs of failure. The three seismic fortification lines of the energy-saving block, internal multiribbed frame, and outer multiribbed frame sequentially played important roles. With the increase in axial compression ratio, the peak bearing capacity and ductility of the wall increased, whereas the initial stiffness decreased. The change in axial compression ratio had a small effect on the energy dissipation capacity of the wall. In the early stage of loading, the influence of axial compression ratio on wall stiffness and strength degradation was unremarkable. In the later stage of loading, the stiffness and strength degradation of walls with high axial compression ratio were low. The displacement ductility coefficients of the wall under vertical pressure were more than 3.0 indicating that this wall type has good deformation ability. The limit values of elastic displacement angle under weak earthquake and elastic-plastic displacement angle under strong earthquake of the EBIMFCW were1/800 and 1/80, respectively.

Simulating three dimensional wave run-up over breakwaters covered by antifer units

  • Najafi-Jilani, A.;Niri, M. Zakiri;Naderi, Nader
    • International Journal of Naval Architecture and Ocean Engineering
    • /
    • 제6권2호
    • /
    • pp.297-306
    • /
    • 2014
  • The paper presents the numerical analysis of wave run-up over rubble-mound breakwaters covered by antifer units using a technique integrating Computer-Aided Design (CAD) and Computational Fluid Dynamics (CFD) software. Direct application of Navier-Stokes equations within armour blocks, is used to provide a more reliable approach to simulate wave run-up over breakwaters. A well-tested Reynolds-averaged Navier-Stokes (RANS) Volume of Fluid (VOF) code (Flow-3D) was adopted for CFD computations. The computed results were compared with experimental data to check the validity of the model. Numerical results showed that the direct three dimensional (3D) simulation method can deliver accurate results for wave run-up over rubble mound breakwaters. The results showed that the placement pattern of antifer units had a great impact on values of wave run-up so that by changing the placement pattern from regular to double pyramid can reduce the wave run-up by approximately 30%. Analysis was done to investigate the influences of surface roughness, energy dissipation in the pores of the armour layer and reduced wave run-up due to inflow into the armour and stone layer.

Dynamic analysis of the agglomerated SiO2 nanoparticles-reinforced by concrete blocks with close angled discontinues subjected to blast load

  • Amnieh, Hassan Bakhshandeh;Zamzam, Mohammad Saber
    • Structural Engineering and Mechanics
    • /
    • 제65권1호
    • /
    • pp.121-128
    • /
    • 2018
  • Three structure-dependent integration methods with no numerical dissipation have been successfully developed for time integration. Although these three integration methods generally have the same numerical properties, such as unconditional stability, second-order accuracy, explicit formulation, no overshoot and no numerical damping, there still exist some different numerical properties. It is found that TLM can only have unconditional stability for linear elastic and stiffness softening systems for zero viscous damping while for nonzero viscous damping it only has unconditional stability for linear elastic systems. Whereas, both CEM and CRM can have unconditional stability for linear elastic and stiffness softening systems for both zero and nonzero viscous damping. However, the most significantly different property among the three integration methods is a weak instability. In fact, both CRM and TLM have a weak instability, which will lead to an adverse overshoot or even a numerical instability in the high frequency responses to nonzero initial conditions. Whereas, CEM possesses no such an adverse weak instability. As a result, the performance of CEM is much better than for CRM and TLM. Notice that a weak instability property of CRM and TLM might severely limit its practical applications.

의료영상의 JPEG2000 압축을 위한 저전력 DWT 프로세서의 설계 및 구현 (Design and Implementation of Low-Power DWT Processor for JPEG2000 Compression of Medical Images)

  • 장영범;이원상;유선국
    • 대한전기학회논문지:시스템및제어부문D
    • /
    • 제54권2호
    • /
    • pp.124-130
    • /
    • 2005
  • In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

CDMA 이동통신 시스템용 기지국 변조기 ASIC 설계 및 구현 (Design and implementation of a base station modulator ASIC for CDMA cellular system)

  • 강인;현진일;차진종;김경수
    • 전자공학회논문지C
    • /
    • 제34C권2호
    • /
    • pp.1-11
    • /
    • 1997
  • We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

  • PDF

Electrical Behaviors of ZnO Elements under Combined Direct and Alternating Voltages

  • Yang, Soon-Man;Lee, Bok-Hee;Paek, Seung-Kwon
    • Journal of Electrical Engineering and Technology
    • /
    • 제4권1호
    • /
    • pp.111-117
    • /
    • 2009
  • This paper presents the characteristics of leakage currents flowing through zinc oxide (ZnO) surge arrester elements under the combined direct-current (DC) and 60 Hz alternating-current (AC) voltages. The current-voltage characteristic curves (I-V curves) of the commercial ZnO surge arrester elements were obtained as a function of the voltage ratio a. At constant peak value of the combined DC and AC voltage, the resistive leakage current of the ZnO blocks was significantly increased as the voltage ratio $\alpha$ increased. The I-V curves under the combined DC and AC voltages were placed between the pure DC and AC characteristics, and the cross-over phenomenon in both the I-V curves and R-V curves was observed at the low current region. The ZnO power dissipation for DC voltages was less than that for AC voltage in the pre-breakdown region and reversed at higher voltages.

열사이클을 적용한 고온 조건 콘크리트 블록의 열용량 특성 (Thermal Energy Capacity of Concrete Blocks Subjected to High-Temperature Thermal Cycling)

  • 양인환;박지훈
    • 한국건설순환자원학회논문집
    • /
    • 제8권4호
    • /
    • pp.571-580
    • /
    • 2020
  • 본 연구에서는 열에너지 저장시스템의 중요한 요소인 저장 매체에 관한 연구를 수행하였다. 열에너지 저장 매체로써 콘크리트는 열적 및 역학적 특성이 우수하며 저렴한 비용으로 인해 다양한 이점을 갖는다. 또한, 강섬유가 혼입된 초고강도 콘크리트는 고인성 및 고강도 특성으로 인해 고온 노출에 우수한 내구성을 나타내며, 강섬유의 높은 열전도율은 축열 및 방열에 유리한 영향을 미친다. 초고강도 콘크리트의 온도분포 특성을 파악하기 위하여 콘크리트 블록을 제작하고 일정한 열사이클을 적용하여 가열실험을 수행하였다. 열유체 흐름에 의한 열전달을 위하여 열전달 파이프를 콘크리트 블록 중심부에 매립하였다. 또한, 열전달 파이프 형상에 따른 온도분포 특성을 비교하기 위하여 핀의 유무에 따라 원형 파이프 및 종방향 핀 부착 파이프를 설정하였다. 열사이클에 따른 온도분포 특성을 분석하고, 이를 토대로 시간에 따른 열에너지 및 누적 열에너지를 산정하여 비교 분석하였다. 열사이클이 반복될수록 강섬유 혼입 초고강도 콘크리트는 고온에 대하여 안정화를 나타내었다. 또한, 온도분포 및 열에너지 산정 결과를 통해 축열 성능을 보유한 것으로 판단되며, 열에너지 저장 매체 역할을 수행할 수 있는 재료로 기대된다.

관통형 연결재로 연결된 PC 보-기둥 맞댐 접합의 내진성능에 관한 실험적 연구 (Seismic Performance of Precast Beam-Column Joints with Thru-Connectors)

  • 박순규;김민희
    • 콘크리트학회논문집
    • /
    • 제22권4호
    • /
    • pp.441-450
    • /
    • 2010
  • 건식공법이 가능하도록 기존의 접합 방식과 차별화 되는 PC 보-기둥 접합부를 개발하여 실용화하기 위한 기초 연구이다. 연속된 PC 기둥 양편에 위치한 보의 접합 단부를 고강도 관통형 연결재로 긴장하여 연결하는 'PC 보-기둥 맞댐 접합(BCJ_TB : precast beam column joints connected with thru-connects)'을 고안하고 실험적 연구를 수행하여 강도저하, 초기강성, 강성저하, 에너지소산능력 등의 내진성능을 분석하였다. 실험 결과에 기둥에서는 손상이 발생하지 않고 보 단부에서 압축파괴가 발생하는데, 이는 비부착 연결재의 초기긴장과 비부착 효과에 의하여 보 단부 콘크리트에 압축응력이 증가하기 때문인 것으로 분석되었다. 보 접합 단부에 CFRP로 구속 효과를 준 접합부의 성능이 상대적으로 우수하였고 네오프렌 패드로 보 기둥 접합면을 연결한 것이 다른 것에 비하여 초기강성을 제외하고는 우수한 내진성능을 보이는 것으로 분석되었다. 비부착 연결재를 사용한 접합부의 파괴모드를 개선하기 위하여 보 단부 콘크리트의 압축 성능을 향상시키고, 연결재의 변위를 적절히 조절할 수 있는 방법이 요구된다.

패턴 형상을 고려한 회전하는 타이어의 온도 예측을 위한 유한 요소 해석 (Finite Element Analysis for Temperature Distribution Prediction of Steady Rolling Tires with Detailed Tread Pattern)

  • 정경문;강성주;박우철;김형석;김기운
    • 한국자동차공학회논문집
    • /
    • 제22권1호
    • /
    • pp.117-125
    • /
    • 2014
  • The temperature distribution of steady state rolling tires with detailed tread blocks is numerically predicted using the three dimensional full patterned tire model. A three dimensional periodic patterned tire model is constructed by copying 1-sector mesh in the circumferential direction. Using the static tire contact analysis, the strain cycles during one revolution are approximated with the strains at Guassian points of the elements which are sector-wise repeated within the same circular ring of elements, by neglecting the tire rolling effect. Based upon the multi-axial fatigue theory, the maximum principal strain is used to represent the combined effect of six strain components on the hysteretic loss. In the following, the deformation due to the inflation and vertical load is calculated using ABAQUS. Then heat generation rate in each element is calculated using an in-house code. Lastly, temperature distribution is calculated using ABAQUS again. Through the numerical experiments, the validity of the proposed prediction method is examined by comparing with the experiment and the temperature distribution of a patterned tire model is compared with those of the main-grooved simple tire model.

CMOS 상보형 구조를 이용한 아날로그 멀티플라이어 설계 (Design of A CMOS Composite Cell Analog Multiplier)

  • 이근호;최현승;김동용
    • 전자공학회논문지SC
    • /
    • 제37권2호
    • /
    • pp.43-49
    • /
    • 2000
  • 본 논문에서는 저전압 저전력 시스템에 응용 가능한 CMOS 4상한 아날로그 멀티플라이어를 제안하였다. 제안된 멀티플라이어는 저전압에서 동작이 용이하며 아날로그 회로를 설계하는데 자주 이용되는 LV(Low-Voltage) 상보형 트랜지스터 방식의 특성을 이용하였다. LV 상보형 구조는 등가 문턱전압을 감소시킴으로서 회로의 동작전압을 감소시킬 수 있는 특징이 있다. 설계된 회로의 특성은 2V 공급전압하에서 0.6㎛ CMOS 공정파라미터를 갖는 HSPICE 시뮬레이션을 통하여 측정되었다. 이때 ±0.5V까지의 입력선형 범위내에서 선형성에 대한 오차는 1%미만이었다. 또한 -3㏈ 점에서의 대역폭은 290㎒, 그리고 전력소모는 373㎼값을 나타내었다.

  • PDF