• Journal of Korea Multimedia Society
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• v.10 no.5
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• pp.583-593
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• 2007

We study the page replacement algorithms for demand paging, called CFLRU/C, CFLRU/E and DL-CFLRU/E, that reduce the number of erase operations and improve the wear-leveling degree of flash memory. Under the CFLRU/C and CFLRU/E algorithms, the victim page is the least recently used dean page within the pre-specified window. However, when there is not any dean page within the window, the CFLRU/C evicts the dirty page with the lowest frequency while the CFLRU/E evicts the dirty page with the highest number of erase operations. The DL-CFLRU/E algorithm maintains two page lists called the dean page list and the dirty page list, and first finds the page within the dean page list when it selects a victim. However, when it can not find any dean page within the dean page list, it evicts the dirty page with the highest number of erase operations within the window of the dirty page list. In this thesis, we show through simulation that the proposed schemes reduce the number of erase operations and improve the wear-leveling than the existing schemes like LRU.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.7-14
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• 2017

Due to the recent advances in Phage-Change Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

• Journal of KIISE
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• v.42 no.9
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• pp.1071-1077
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• 2015

In this paper, we adopt PCM (phase-change memory) as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among the pages not recently used. Experimental results show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.634-641
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• 2006

Flash memory has many advantages like non-volatility and fast I/O speed, but it has also disadvantages such as not-in-place-update data and asymmetric read/write/erase speed. For the performance of flash memory storage, it is essential for the buffer replacement algorithms to reduce the number of write operations that also affects the number of erase operations. A new buffer replacement algorithm is proposed in this paper, that delays the writes of not-cold-dirty pages in the buffer cache of flash storage. We show that this algorithm effectively decreases the number of write operations and erase operations without much degradation of hit ratio. As a result overall performance of flash I/O speed is improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.412-421
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• 2009

Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, and therefore erase operations are required prior to rewriting. These extra operations cause performance degradation of NAND flash memory file system. Since it also has an upper limit to the number of erase operations for a specific location, frequent erases should reduce the lifetime of NAND flash memory. These problems can be resolved by delaying write operations in order to improve I/O performance: however, it will lower the cache hit ratio. This paper proposes a policy of page management using double cache for NAND flash memory file system. Double cache consists of Real cache and Ghost cache to analyze page reference patterns. This policy attempts to delay write operations in Ghost cache to maintain the hit ratio in Real cache. It can also improve write performance by reducing the search time for dirty pages, since Ghost cache consists of Dirty and Clean list. We find that the hit ratio and I/O performance of our policy are improved by 20.57% and 20.59% in average, respectively, when comparing them with the existing policies. The number of write operations is also reduced by 30.75% in average, compared with of the existing policies.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.161-170
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• 2022

Recently, NAND-type flash memory has been regarded to be new promising storage media for large-scale database systems. For flash memory to be employed for that purpose, we need to reduce its expensive update cost caused by the inablity of in-place updates. To remedy such a drawback in flash memory, we propose a new flash-aware buffering scheme that enables virtual flushing of dirty pages. To this end, we slightly alter the tradional algorithms used for the logging scheme and buffer management scheme. By using the mechanism of virtual flushing, our proposed buffering scheme can efficiently prevent the frequenct occureces of page updates in flash storage. Besides the advantage of reduced page updates, the proposed viurtual flushing mechanism works favorably for shorneing a recocery time in the presense of failure. This is because it can reduce the time for redo actions during a recovry process. Owing to those two benefits, we can say that our scheme couble be very profitable when it is incorporated into cutting-edge flash-based database systems.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.235-244
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• 2007

Caching and prefetching policies have been used in most of computer systems to compensate speed differences between primary memory and secondary storage devices. In this paper, we design and implement a Flash Cache Core Module(FCCM) on the YAFFS which operates on a file system layer for NAND flash memory. The FCCM is independent of the underlying kernel in order to support its stability and compatibility. Also, we implement the Dirty-Last memory replacement technique considering the characteristics of flash memory, and the waiting queue for pages to be prefetched according to page hit. The FCCM reduced the number of I/Os and the amount of prefetched pages by maximum 55%(20% on average) and maximum 55%(24% on average), respectively, comparing with caching and prefetching policies of Linux.

• The KIPS Transactions:PartD
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• v.16D no.6
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• pp.825-834
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• 2009

최근에 낸드 플래시 메모리는 빠른 접근속도, 저 전력 소모, 높은 내구성 등의 특성으로 인하여 차세대 대용량 저장 매체로 각광 받고 있다. 그러나 디스크 기반의 저장 장치와는 달리 비대칭적인 읽기, 쓰기, 소거 연산의 처리 속도를 가지고 있고 제자리 갱신이 불가능한 특성을 가지고 있다. 따라서 디스크 기반 시스템의 버퍼 교체 정책은 플래시 메모리 기반의 시스템에서 좋은 성능을 보이지 않을 수 있다. 이러한 문제를 해결하기 위해 플래시 메모리의 특성을 고려한 새로운 플래시 메모리 기반의 버퍼 교체 정책이 제안되어 왔다. 본 논문에서는 디스크 기반의 저장 장치에서 우수한 성능을 보인 CLOCK-Pro를 낸드 플래시 메모리의 특성을 고려하여 개선한 CLOCK-NAND를 제안한다. CLOCK-NAND는 CLOCK-Pro의 알고리즘에 기반하며, 추가적으로 페이지 접근 정보를 효율적으로 활용하기 위한 새로운 핫 페이지 변경을 한다. 또한, 더티인 핫 페이지에 대해 콜드 변경 지연 정책을 사용하여 쓰기 연산을 지연하며, 이러한 새로운 정책들로 인하여 낸드 플래시 메모리에서 쓰기 연산 횟수를 효율적으로 줄이는 우수한 성능을 보인다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.85-91
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• 2019

In this paper, we propose a new logging and recovery scheme that is suited for the high-performance transaction processing system base on flash memory storage. The proposed scheme is designed by considering flash's I/O characteristic of asymmetric costs between page update/read operations. That is, we substitute the costly update operation with writing and real-time usage of snapshot log, which is for the page-level physical redo. From this, we can avoid costly rewriting of a dirty page when it is evicted form a buffering pool. while supporting efficient revery procedure. The proposed scheme would be not lucrative in the case of HDD-based system. However, the proposed scheme offers the performance advance sush as a reduced number of updates and the fast system recovery time, in the case of flash storage such as SSD (solid state drive). Because the proposed scheme can easily be applied to existing systems by saving our snapshot records and ordinary log records together, our scheme can be used for improving the performance of upcoming SSD-based database systems through a tiny modification to existing REDO algorithms.