• 천문학회보
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• 제36권2호
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• pp.125.2-125.2
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• 2011

We are developing medium resolution cross-dispersed silicon grisms in the near IR region ($1.45{\sim}5.2{\mu}m$). The grisms will be installed in MIMIR, a multifunction instrument at the Lowel Observatory, USA. The two devices are designed to cover H and K band and L and M band simultaneously. Our goal is to make grism with R=3000 at 1.2 arcsec slit. The Silicon has high refractive index (n=3.4 at $1.5{\mu}m$) which enhances the resolving power by up to 5 times when compared to conventional material such as BK-7 (n=1.5 at 1.5 ${\mu}m$). The bonded grisms will be installed in a filter wheel for the uses switch from spectroscopic mode to imaging mode easily. Our device is compact and light weighted while it provides a decent resolving power. We produce monolithic grisms using e-beam lithography at the NASA JPL and chemically etching the grooves on the silicon prisms. Moreover, the main-disperser and cross-disperser will be contacted together by direct Si-Si bonding technique and eventually turn into one piece. The bonded pair offers more stability in terms of the layout of the spectrum and removes the Fresnel loss at the intersection of two grisms. We report on the proper wafer bonding steps through this research, and inspected the bonding quality thermally, optically and mechanically.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• 한국표면공학회지
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• 제33권2호
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• 센서학회지
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• 제14권3호
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• pp.206-210
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• 2005

The SOI structure with buried alumina was fabricated by ALD followed by bonding and etchback process. The interface of alumina and silicon was analyzed by CV measurements and cross section was investigated by SEM analysis. The density of interface state of alumina and silicon was 2.5E11/$cm^{2}$-eV after high temperature annealing for wafer bonding. It was confirmed that the surface silicon layer was completely isolated from substrate by cross section SEM and AES depth profile. The device on this alumina SOI structure would have better thermal properties than that on conventional SOI due to higher thermal conductivity of alumina than that of silicon dioxide.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1431-1433
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• 1995

This paper describes the characteristics of Si Hall sensors fabricated on a SOI(Si-on-insulator} structure, in which the SOI structure was forrmed by SDB(Si-wafer direct bonding) technology. The Hall voltage and the sensitivity of implemented Si Hall devices show good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average $600V/A{\cdot}T$. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the product Sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. From these results, Si Hall sensors using the SOI structure presented here are very suitable for high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.2023-2025
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• 2002

We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

• 센서학회지
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• 제3권3호
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• pp.45-53
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• 1994

실리콘의 직접 접합 방법과 2단계 전기화학적 식 정지 방법을 이용하여 새로운 구조의 실리콘 다이아프램을 제조하였다. 이러한 다이아프램 구조를 기계량 센서에 이용하면 공동의 깊이와 다이아프램의 두께를 보다 정교하게 조절할 수 있다. 또한, 접합 계면에서 발생하는 응력이 다이아프램의 표면으로 전달되는 것을 피할 수 있다. 최종적으로, 제조된 다이아프램을 이용하여 암저항형 실리콘 압력 센서를 제작하였고 압력 단위의 표시가 가능한 디지탈 압력 측정기를 구현하였다.

• 센서학회지
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• 제13권4호
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• pp.264-269
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• 2004

This paper describes on an advanced technology of 3C-SiC/Si(100) wafer direct bonding using PECVD oxide to intermediate layer for SiCOI(SiC-on-Insulator) structure because it has an attractive characteristics such as a lower thermal stress, deposition temperature, more quick deposition rate and higher bonding strength than common used poly-Si and thermal oxide. The PECVD oxide was characterized by ATR-FTIR. The bonding strength with variation of HF pre treatment condition was measured by tensile strength measurement system. After etch-back using TMAH solution, roughness of 3CSiC surface crystallinity and bonded interface was measured and analyzed by AFM, XRD, and SEM respectively.

• 한국정밀공학회지
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• 제26권12호
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• pp.9-17
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• 2009