• Title/Summary/Keyword: Direct Wafer Bonding

Search Result 110, Processing Time 0.027 seconds

The Fabrications of Vertical Trench Hall-Effect Device for Non-contact Angular Position Sensing Applications (비 접촉 각도 센서 응용을 위한 수직 Hall 소자의 제작)

  • Park, Byung-Hwee;Jung, Woo-Chul;Nam, Tae-Chul
    • Proceedings of the KIEE Conference
    • /
    • 2002.11a
    • /
    • pp.251-253
    • /
    • 2002
  • We have fabricated a novel Vertical Trench Hall-Effect Device sensitive to the magnetic field parallel to the sensor chip surface for non-contact angular position sensing applications. The Vertical Trench Hall-Effect Device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 150 V/AT is measured.

  • PDF

Direct Bonding of SiN/SiO Silicon wafer pairs (직접접합 질화규소/산화규소절연막 이종실리콘기판쌍의 제조)

  • 이상현;서태윤;송오성
    • Proceedings of the KAIS Fall Conference
    • /
    • 2001.11a
    • /
    • pp.169-172
    • /
    • 2001
  • 다층 MEMS구조의 기초기판쌍 소재로 쓰일 수 있는 Si∥SiO₂/Si₃N₄∥Si 기판쌍의 직접접합 가능성을 확인하기 위해서 2000Å-SiO₂와 500Å-Si₃N₄층을 가진 직경 10cm의 실리콘 기판을 각각 친수성 및 소수성 표면세척을 하고 청정분위기에서 경면끼리 가접을 실시하였다. 가접된 기판쌍을 통상의 박스형 전기로를 이용하여 400, 600, 800, 1000, 1200℃ 범위에서 2시간 동안 가열하여 접합을 완료하였다. 완성된 기판쌍을 적외선분석기를 이용하여 접합면적을 확인하였고, 면도칼 삽입법으로 접합계면에너지를 측정하였다. 실험온도 범위 내에서 Si∥SiO₂/Si₃N₄∥Si 기판쌍은 1000℃ 이상에서 접합계면에너지는 2,344mJ/㎡을 나타냈으며, 이는 기존의 Si/Si의 동종접합기판쌍과 동등한 수준의 접합강도로서 부가가치가 큰 새로운 조합의 기판쌍 제조가 가능하였다.

Fabrication and Characteristics Comparison of Piezoresistive Four Beam Silicon Accelerometer Based on Beam Location (빔 위치변화에 따른 4빔 압저항형 실리콘 가속도 센서의 제조 및 특성비교)

  • Shin, Hyun-Ok;Son, Seung-Hyun;Choi, Sie-Young
    • Journal of the Korean Institute of Telematics and Electronics D
    • /
    • v.36D no.7
    • /
    • pp.26-33
    • /
    • 1999
  • In order to examine the effect of beam location n the performance of bridge type piozoresistive silicon accelerometer, three sensors having different location of beams were simulated by FEN(finite element method) and fabricated by RIE(reactive ion etching) and KOH etching method using SDB(silicon direct bonding) wafer, Results of the FEM simulation present that the 1st resonace frequency and Z axis sensitivity of each sensor are identical but the 2nd, and the 3rd resonace frequency and X, Y axis sensitivity are different. Even though the 1st resonance frequency and Z axis sensitivity measured from fabricated sensors do not perfectly coincide with each other, all 3 type sensors present 180 ~ 220N/G of Z sensitivity at 5 V supply voltage and 1.3 ~ 1.7kHz of the 1st resonance frequency and about 2% of lateral sensitivity.

  • PDF

The Removal Of Voids In The Grooved Interfacial Region Of Silicon Structures Obtained With Direct Bonding Technique (홈구조 실리콘 접합 경계면에서의 Void 제거를 위한 실리콘 직접접합 방법)

  • Kim, Sang-Cheol;Kim, Eun-Dong;Kim, Nam-Kyun;Bahna, Wook;Soo, Gil-Soo;Kim, Hyung-Woo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2002.07a
    • /
    • pp.310-313
    • /
    • 2002
  • Structures obtained with a direct boning of two FZ silicon wafers joined in such a way that a smooth surface of one wafer was attached to the grooved surface of the other were studied. A square net of grooves was made with a conventional photo lithography process. After high temperature annealing the appearance of voids and the rearrangement of structural defects were observed with X-ray diffraction topography techniques. It was shown that the formation of void free grooved boundaries was feasible. In the cases when particulate contamination was prevented, the voids appeared in the grooved structures could be eliminated with annealing. Since it was found that the flattening was accompanied with plastic deformation, this deformation was suggested to be intensively involved in the process of void removal. A model was proposed explaining the interaction between the structural defects resulted in "a dissolution" of cavities. The described processes may occur in grooved as well as in smooth structures, but there are the former that allow to manage air traps and undesirable excess of dislocation density. Grooves can be paths for air leave. According to the established mechanisms, if not outdone, the dislocations form local defect arrangements at the grooves permitting the substantial reduction in defect density over the remainder of the interfacial area.

  • PDF

Analysis of Shear Stress Type Piezoresistive Characteristics in Silicon Diaphragm Structure (실리콘 다이아프램 구조에서 전단응력형 압전저항의 특성 분석)

  • Choi, Chae-Hyoung;Choi, Deuk-Sung;Ahn, Chang-Hoi
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.25 no.3
    • /
    • pp.55-59
    • /
    • 2018
  • In this paper, we investigated the characteristics of shear stress type piezoresistor on a diaphragm structure formed by MEMS (Microelectromechanical System) technology of silicon-direct-bonding (SDB) wafers with Si/$SiO_2$/Si-sub. The diaphragm structure formed by etching the backside of the wafer using a TMAH aqueous solution can be used for manufacturing various sensors. In this study, the optimum shape condition of the shear stress type piezoresistor formed on the diaphragm is found through ANSYS simulation, and the diaphragm structure is formed by using the semiconductor microfabrication technique and the shear stress formed by boron implantation. The characteristics of the piezoelectric resistance are compared with the simulation results. The sensing diaphragm was made in the shape of an exact square. It has been experimentally found that the maximum shear stress for the same pressure at the center of the edge of the diaphragm is generated when the structure is in the exact square shape. Thus, the sensing part of the sensor has been designed to be placed at the center of the edge of the diaphragm. The prepared shear stress type piezoresistor was in good agreement with the simulation results, and the sensitivity of the piezoresistor formed on the $2200{\mu}m{\times}2200{\mu}m$ diaphragm was $183.7{\mu}V/kPa$ and the linearity of 1.3 %FS at the pressure range of 0~100 kPa and the symmetry of sensitivity was also excellent.

Direct bonding of Si(100)/Si$_3$N$_4$∥Si (100) wafers using fast linear annealing method (선형열처리를 이용한 Si(100)/Si$_3$N$_4$∥Si (100) 기판쌍의 직접접합)

  • Lee, Young-Min;Song, Oh-Song;Lee, Sang-Hyun
    • Korean Journal of Materials Research
    • /
    • v.11 no.5
    • /
    • pp.427-430
    • /
    • 2001
  • We prepared 10cm-diameter Si(100)/500 $\AA$-Si$_3$N$_4$/Si(100) wafer Pairs adopting 500 $\AA$ -thick Si$_3$N$_4$layer as insulating layer between single crystal Si wafers. Si3N, is superior to conventional SiO$_2$ in insulating. We premated a p-type(100) Si wafer and 500 $\AA$ -thick LPCVD Si$_3$N$_4$∥Si (100) wafer in a class 100 clean room. The cremated wafers are separated in two groups. One group is treated to have hydrophobic surface and the other to have hydrophilic. We employed a FLA(fast linear annealing) bonder to enhance the bond strength of cremated wafers at the scan velocity of 0.1mm/sec with varying the heat input at the range of 400~1125W. We measured bonded area using a infrared camera and bonding strength by the razor blade crack opening method. We used high resolution transmission electron microscopy(HRTEM) to probe cross sectional view of bonded wafers. The bonded area of two groups was about 75%. The bonding strength of samples which have hydrophobic surface increased with heat input up to 1577mJ/$m^2$ However, bonding strength of samples which have hydrophilic surface was above 2000mJ/$m^2$regardless of heat input. The HRTEM results showed that the hydrophilic samples have about 25 $\AA$ -thick SiO layer between Si and Si$_3$N$_4$/Si and that maybe lead to increase of bonding strength.

  • PDF

Fabrication of SOI Structures with Buried Cavities for Microsystems SDB and Electrochemical Etch-stop (SDB와 전기화학적 식각정지에 의한 마이크로 시스템용 매몰 공동을 갖는 SOI 구조의 제조)

  • Chung, Gwiy-Sang;Kang, Kyung-Doo;Choi, Sung-Kyu
    • Journal of Sensor Science and Technology
    • /
    • v.11 no.1
    • /
    • pp.54-59
    • /
    • 2002
  • This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.

Fabrication of a Micro Multilayer Piezo Actuator Valve and Its Characteristics (마이크로 적층형 압전밸브의 제작과 그 특성)

  • Chung, Gwiy-Sang;Kimm, Jae-Min;Cho, Sang-Bock
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.913-916
    • /
    • 2005
  • This paper describes the design, fabrication and characteristics of a piezoelectric valve using MCA(Multilayer ceramic actuator). The MCA valve, which has the buckling effect, consists of three separate structures; MCA, a valve actuator die and an a seat die. The design of the actuator die was done by FEM modeling and displacement measurement, respectively. The valve seat die with 6 trenches was made, and the actuator die, which is driven to MCA under optimized conditions, was also fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the seat/actuator die structure. PDMS sealing pad was fabricated to minimize a leak-rate. It was also bonded to seat die and SUS package. The MCA valve shows a flow rate of 9.13 sccm at a supplied voltage of 100 V with a 50 % duty cycle, maximum non-linearity was 2.24 % FS and leak rate was $3.03{\times}10^{-8}pa$. $m^3/cm^2$.

  • PDF

Fabrication of a Silicon Hall Sensor for High-temperature Applications (고온용 실리콘 홀 센서의 제작)

  • 정귀상;류지구
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.13 no.6
    • /
    • pp.514-519
    • /
    • 2000
  • This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$as a dielectrical isolation layer a SDB SOI Hall sensor without pn junction has been fabricated on the Si/ $SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to 30$0^{\circ}C$ the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm$6.7$\times$10$_{-3}$ and $\pm$8.2$\times$10$_{-4}$$^{\circ}C$ respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

  • PDF

Fabrication of a Silicon Hall Sensor for High-temperature Applications (고온용 실리콘 홀 센서의 제작)

  • Chung, Gwiy-Sang;Ryu, Ji-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2000.05b
    • /
    • pp.29-33
    • /
    • 2000
  • This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

  • PDF