• 한국통신학회:학술대회논문집
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• 한국통신학회 1988년도 추계학술발표회 논문집
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• pp.101-108
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• 1988

In this paper packet-swap Accptant Queveing system with synchronous single server and finite storage space is proposed for throughput improvement. Queueling systems are analyzed with Minisint Approximation reported by J.F CHANG and R.F Chang. Comparison between PSA. Queveing system and First-Come First Acceptant Queveing system via throughput and blocking probabilliy of test octet was performed The comparison showed that PAS Queweing system perfumes better than j.F ChANG’s Queveing system.

• 한국멀티미디어학회:학술대회논문집
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• 한국멀티미디어학회 2012년도 춘계학술발표대회논문집
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• pp.451-451
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• 2012

• Journal of information and communication convergence engineering
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• 제6권1호
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• pp.47-50
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• 2008

A novel high channel efficiency transceiver based on a fast acquisition frequency synthesizer has been designed. The direct digital synthesis (DDS) technique is applied and a simple memory look-up table is incorporated to expedite channel acquisition. The technique simplifies the frequency control process in the transceiver and thus reduces the channel switching time. As a result, the channel efficiency is improved. The designed transceiver is ideal for frequency hopping mobile communication applications.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• 한국통신학회논문지
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• 제16권10호
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• pp.914-924
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• 1991

랜덤한 주파수도약을 실현하기 위해 기존의 PLL(Phase Locked Loop)방식이 많이 사용 되었으나 locking time이 소요되는바, 출력주파수의 졍현파형을 직접 합성하는 직접 디지털 주파수 합성방식을 이용하여 이러한 단점을 없앨 수 있으나. 기존의 위상누적 방식을 이용한 직접 디지털 주파수 합성방식에서는 합성 파형상에 위상 왜곡이 수반되어 불요잡음이 크게 나타났다. 이러한 단점을 개선하기 위해 위상누적 방식에 관한 이론을 고찰하고 새로운 방식의 이론식을 유도하여 이에 적합한 시스템을 구성하였다. 또한 합성된 출력주파수의 정현파형에 대한 스펙트럼 분석과 PN(pseudo Noise)부호를 사용한 순시적인 주파수 도약상태의 확인 결과, 기존의 위상누적 방식보다 불요잡음 전력레벨이 10~25dB 줄고 주파수 대역도 420kHz까지 확장 가능함을 알았다.

• 한국전자파학회논문지
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• 제21권3호
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• pp.321-330
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• 2010

본 논문에서는 컴프레시브 RFID 신호를 탐지하기 위한 컴프레시브 수신기의 이론적 배경과 구체적 구현 방법, 그리고 분산 지연선과 chirp LO의 설계 방안에 대해 기술하였다. 컴프레시브 수신기의 주요 구성품 중 하나인 분산 지연선을 대역폭 6 MHz, 분산 지연 시간 $13{\mu}s$으로 설계하여 $LiNbO_3$ 재질 기반의 SAW(Surface Acoustic Wave) 기술을 통해 구현하였고, DDS(Direct Digital Synthesizer)를 이용하여 chirp LO를 구현하였다. 또한 RFID 리더에 내장되어 연동될 수 있도록 컴프레시브 수신기를 구성하였다. 시험 결과, 단일 신호 입력시 주파수 오차는 최대 25 kHz, 수신 감도는 -44 dBm, 500 kHz 간격으로 동시에 입력되는 6개의 신호에 대한 주파수 오차는 최대 75 kHz로서 제작된 컴프레시브 수신기가 밀집된 RFID 운영 환경에 적합함을 보였다.

• 전자공학회논문지D
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• 제34D권3호
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• pp.41-51
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• 1997

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.

• 전자공학회논문지C
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• 제34C권8호
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• pp.1-7
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• 1997

In tis paper, w eproposed a modeling for direct-sequence spread communication base band modem in RT-level VHDL and implemented in a one-chip VLSI and tested. The transmitter modulates with DQPSK modulation method and spreads a modulated signal with 32-bit PN code into 1.152MHz. The receiver de-spreads a signal using 32-tap matched filter and recovers with DQPSK demodulation method. The digital frequency synthesizer generates the sine signal and the cosine signal of 2.304MHz with ROM tables in the size of 7$\^$*/256 and 6$\^$*/256, respectively. The implemented VLSI has been verified a BER with 10$\^$-4/ at E$\_$b//N$\_$o/ of 13dB with a SPW fixed design model and fabricated in the 0.8.mu.m KG6423 gate array with a VHDL model.

• 한국군사과학기술학회지
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• 제19권3호
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.