• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.32-39
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• 2009

Compressed Sensing is a method to sample analog signals at a rate under the Nyquist rate. With this scheme, it is possible to represent signals with a relatively smaller number of measurements than that of the conventional sampling method, and the original signals are reconstructed with high probability from the acquired measurements using the linear programming. Compressed sensing allows measurement time and/or the amount of ADC (analog-to-digital converter) resources for the signal acquisitions to be reduced. In this paper, we presents the backgrounds of the compressed sensing, a way to acquire measurements from an analog signal with a random basis, and the signal recovery method. Also we introduce applications of compressed sensing in wireless communications.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.256-261
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• 2011

In this paper, a design and an implementation of an Analog to Digital (A/D) converter are introduced for the conversion of monitored battery cell voltage in the cell voltage monitoring(CVM) system in battery management system(BMS), which is one of the key devices of ECO hybrid cars. The A/D converter in CVM system required a middle conversion speed and a high resolution, therefore, a successive approximate register(SAR) typed A/D converter with 10 bits resolution has been designed and implemented using Magna 0.6um 40V process. The measurement result which kept ${\pm}1$ LSB accuracy in the full scale range(FSR) of 5V, showed the usefulness of the SAR typed A/D converter in realizing a CVM system.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.219-222
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• 2003

The Capacitor DAC with gamma correction is proposed for TFT-LCD (Liquid Crystal Display) driver application. It is based on two ideas. First, 6bit digital code is converted 8bit digital code by memory circuit (Look Up Table) for gamma correction. second, weighted voltage ratio DAC is proposed for reducing area and power consumption.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1489-1496
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• 2010

A feed forward differential architecture of analog PRML decoder is investigated to implement on analog parallel processing circuits. The conventional PRML decoder performs the trellis processing with the implementation of single stage in digital and its repeated use. The analog parallel processing-based PRML comes from the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Shortening the trellis processing stages but implementing it with analog parallel circuits, several benefits including higher speed, no memory requirement and no A/D converter requirement are obtained. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback of the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from all the states of the decoding stage, which enables to be decoded without feedback. The circuit of the proposed architecture is simpler than that of the conventional analog parallel processing structure with the similar decoding performance. Characteristics of the feed forward differential architecture are investigated through various simulation studies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• The Journal of the Acoustical Society of Korea
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• v.6 no.3
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• pp.52-59
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• 1987

In this paper, we present a method of realizing an infinite impulse response (IIR) digital filter (DF)using linear delta modulation (LDM) as a simple analog/digital (A/D) converter. This method makes the realization of IIR digital filters much simpler than that of conventional ones because it does not require hardware multipliers and a pulse code modulation (PCM) A/D converter. Compared to the finite impulse respponse (FIR) LDMDF of Lee and Un [1] , this IIR LDMDF requires significantly less computation time.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.882-885
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• 2003

In this paper, nonlinear echo cancellation using a correlation LMS (CLMS) algorithm is proposed to cancel the undesired nonlinear echo signals generated in the hybrid system of the telephone network. In the telephone network, the echo signals may result the degradation of the network performance. Furthermore, digital to analog converter (DAC) and analog to digital converter (ADC) may be the source of the nonlinear distortion in the hybrid system. The adaptive filtering technique based on the nonlinear Volterra filter has been the general technique to cancel such a nonlinear echo signals in the telephone network. But in the presence of the double-talk situation, the error signal for tap adaptations will be greatly larger, and the near-end signal can cause any fluctuation of tap coefficients, and they may diverge greatly. To solve a such problem, the correlation LMS (CLMS) algorithm can be applied as the nonlinear adaptive echo cancellation algorithm. The CLMS algorithm utilizes the fact that the far-end signal is not correlated with a near-end signal. Accordingly, the residual error for the tap adaptation is relatively small, when compared to that of the conventional normalized LMS algorithm. To demonstrate the performance of the proposed algorithm, the DAC of hybrid system of the telephone network is considered. The simulation results show that the proposed algorithm can cancel the nonlinear echo signals effectively and show robustness under the double-talk situations.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.