• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• 한국해양학회지
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• v.27 no.1
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• pp.19-34
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• 1992

Marine seismic refraction surveys have been carried out by Korea Institute of Geology, Mining and Materials(KIGAM) since 1984. The recording of refraction data was based on analog instrumentation. Therefore the resolution of refraction data was not good enough to distinguish many layers. The objective of the interpretation of seismic refraction data is the determination of intervals and critically refracted seismic wave propagation velocities through the layers beneath the sea floor. To determine intervals and velocities precisely, the resolution of refraction data should be enhanced. The intent of the study is to improve the quality of shallow marine refraction data by the digital technique using microcomputer- based acquisition and processing system. The system consists of an IBM AT microcomputer clone, an analog-digital(A/D) converter. A mass storage unit and a parallel processing board. The A/D converter has 12 bits of precision and 250 kHz of conversion rate. The magneto-optical disk drive is used for the mass storage of seismic refraction data. Shallow marine seismic refraction surveys have been carried out using the system at 6 locations off Ulsan and Pusan area. The refraction data were acquired by the radio sonobuoy. The refraction profiles have been produced by the laser printer with 300 dpi resolution after the basic computer processing. 5-9 layers were interpreted from digital refraction profiles, whereas 2-4 layers were interpreted from analog refraction profiles. the propagation velocities of sediments were interpreted as 1.6-2.1 km/sec. The propagation velocities of acoustic basement were interpreted as 2.4-2.7 km/sec off Ulsan area, 4.8 km/sec off Pusan area.

• Journal of IKEEE
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• v.17 no.4
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• pp.511-516
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• 2013

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.

• ETRI Journal
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• v.37 no.6
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• pp.1176-1187
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• 2015

This work proposes a highly efficient sensorless motor driver chip for various permanent-magnet synchronous motors (PMSMs) in a wide power range. The motor driver chip is composed of two important parts. The digital part is a sensorless controller consisting mainly of an angle estimation block and a speed control block. The analog part consists of a gate driver, which is able to sense the phase current of a motor. The sensorless algorithms adapted in this paper include a sliding mode observer (SMO) method that has high robust characteristics regarding parameter variations of PMSMs. Fabricated SMO chips detect back electromotive force signals. Furthermore, motor current-sensing blocks are included with a 10-bit successive approximation analog-to-digital converter and various gain current amplifiers for proper sensorless operations. Through a fabricated SMO chip, we were able to demonstrate rated powers of 32 W, 200 W, and 1,500 W.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1A
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• pp.28-34
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• 2011

In this paper, we proposed the architecture of the Hybrid Quadrature Polar transmitter which has the wideband characteristics available for the SRD(Short Range Device). First, we developed the simulation environment and carried out performance degradation analysis. Second, we considered the slewrate of the VVA(Voltage Variable Attenuator), time delay between magnitude signal and phase signal and the number of bits for DAC(Digital-to-Analog Converter) as the main performance factors. Then we obtained the minimum required values to meet the transmitting performance requirements of 3GPP standards through simulation results. Based on these results, we implemented the Wideband Hybrid Quadrature Polar transmitter platform and varified the performance requirements through practical measurement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.4
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• pp.351-358
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• 2013

We propose a correction method of nonlinear frequency sweep in an FMCW(Frequency Modulated Continuous Wave) laser range finder. FMCW laser range finder requires linear frequency sweep for high resolution, and nonlinear frequency sweep makes the system performance degrade. In general, VCO(Voltage Controlled Oscillator) which is a component used for frequency modulation in FMCW method has nonlinear property. To correct the nonlinear frequency sweep, we utilize an auxiliary delay structure for generating trigger signal of ADC(Analog to Digital Converter). Because the trigger signal has same rate of change with the beat signal, the nonlinearity of the beat signal can be corrected. the experimental results show that the proposed method effectively eliminates the nonlinear frequency sweep problem and enhances the system performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• Korean Journal of Materials Research
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• v.4 no.5
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• pp.502-509
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• 1994

New damping measurement equipment was designed using the dynamic strain gage and high speed analog to digital signal 12 bit converter and compared it with existing equipment. The damping properties of general material and high damping material were also studied by this machine. The SDC (specific damping capacity) was measured with various heat treatment condition, initial vibration amplitude and internal stress. The vibration amplitude of high damping material is decreased within nearly less than 0.4 second after applying the initial forced vibration. But that of general material is still vibrating at the same time. After furnace-cooling heat treatment, SDCmax of Fe-lGwt.%Cr system was more than 40% and that of Fe-5.5wt.%Al alloy was more than 30% after air-cooling heat treatment. Upon increasing of initial vibration amplitude, it is detected the migration of SDCmax into the region of small vibraton amplitude. Damping capacity is decreased rapidly as the internal stress Increases. Damping measurement equipment in the present study was ahln to give the more accurate results of damping properties in the small vibration amplitude region.

• Journal of the Korea institute for structural maintenance and inspection
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• v.18 no.1
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• pp.160-165
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• 2014

In this study, an efficiency test was performed by fabricating MEMS (Micro Electro Mechanical Systems) based 3-axis acceleration sensor modules and an earthquake monitoring system was composed. Data acquisition device (NI-9239) with a 24bit ADC (Analog to Digital Converter) was used for improving the performance of 3-axis acceleration sensor modules and filtered data (100Hz Low Pass Filter) was used for reducing noises. Also this paper focused on detecting meaningful vibration in the building by developing the earthquake monitoring software. If vector sum of 3-axis acceleration is greater than the preset value, the value will be recorded and saved to the file.